Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – On insulating substrate or layer
Reexamination Certificate
2011-05-17
2011-05-17
Dickey, Thomas L (Department: 2826)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
On insulating substrate or layer
C438S128000, C257SE21119
Reexamination Certificate
active
07943493
ABSTRACT:
A contiguous block of a stack of two heterogeneous semiconductor layers is formed over an insulator region such as shallow trench isolation. A portion of the contiguous block is exposed to an etch, while another portion is masked during the etch. The etch removes an upper semiconductor layer selective to a lower semiconductor layer in the exposed portion. The etch mask is removed and the entirety of the lower semiconductor layer within the exposed region is metallized. A first metal semiconductor alloy vertically abutting the insulator region is formed, while exposed surfaces of the stack of two heterogeneous semiconductor layers, which comprises the materials of the upper semiconductor layer, are concurrently metallized to form a second metal semiconductor alloy. An inflection point for current and, consequently, a region of flux divergence are formed at the boundary of the two metal semiconductor alloys.
REFERENCES:
patent: 4679310 (1987-07-01), Ramachandra et al.
patent: 5365105 (1994-11-01), Liu et al.
patent: 5955275 (1999-09-01), Kamb
patent: 5969404 (1999-10-01), Bohr et al.
patent: 6204132 (2001-03-01), Kittl et al.
patent: 6274440 (2001-08-01), Arndt et al.
patent: 6326289 (2001-12-01), Rodder et al.
patent: 6384664 (2002-05-01), Hellums et al.
patent: 6507087 (2003-01-01), Yu
patent: 6642601 (2003-11-01), Marshall et al.
patent: 6661330 (2003-12-01), Young
patent: 6958523 (2005-10-01), Babcock et al.
patent: 6982610 (2006-01-01), Govind
patent: 6984550 (2006-01-01), Yamazaki et al.
patent: 7491585 (2009-02-01), Yang et al.
patent: 7550323 (2009-06-01), Chidambarrao et al.
patent: 2003/0160297 (2003-08-01), Kathandaraman et al.
patent: 2008/0308900 (2008-12-01), Kim et al.
patent: 2009/0040006 (2009-02-01), Chidambarrao et al.
patent: 2009/0042341 (2009-02-01), Chidambarrao et al.
patent: 2009/0051002 (2009-02-01), Booth et al.
patent: 2009/0101989 (2009-04-01), Chen et al.
Chidambarrao Dureseti
Henson William K.
Kim Deok-Kee
Kothandaraman Chandrasekharan
Abate Esq. Joseph P.
Dickey Thomas L
Erdem Fazli
International Business Machines - Corporation
Scully , Scott, Murphy & Presser, P.C.
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