Electrical die contact structure and fabrication method

Details Electrical die contact structure and fabrication method Electrical die contact structure and fabrication method

2002-12-04

2004-08-24

Lee, Hsien Ming (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S780000, C257S781000, C257S782000, C257S784000, C438S108000, C438S118000, C438S119000, C438S612000, C438S613000, C438S614000

Reexamination Certificate

active

06781244

ABSTRACT:

TECHNICAL FIELD
The invention described herein relates generally to semiconductor chip manufacturing processes. In particular, the invention relates to improved electrical contact structures and the methods for their manufacture.
BACKGROUND
One step in the manufacture of integrated circuit devices is known as “packaging” and involves mechanical and environmental protection of a semiconductor chip which is at the heart of the integrated circuit as well as electrical interconnection between predetermined locations on the silicon chip and external electrical terminals.
Presently, a number of conventional technologies are employed for packaging semiconductors. Wire bonding, tape automatic bonding (TAB), and flip chip connection are among the packaging techniques used in the industry.
Wire bonding employs heat and ultrasonic energy to weld gold bonding wires between bond pads on the chip and contacts on the package.
Tape automatic bonding (TAB) employs a copper foil tape instead of bonding wire. The copper foil tape is configured for each specific die and package combination and includes a pattern of copper traces suited thereto. The individual leads may be connected individually or as a group to the various bond pads on the chip.
Flip chips are integrated circuit dies which have solder bumps formed on top of the bonding pads, thus allowing the die to be “flipped” circuit side down and directly soldered to a substrate. Wire bonds are not required and considerable savings in package footprint may be realized.
Additionally, a so-called “T-contact” connector packaging method is employed by some manufacturers. This “T-contact” method is described in some detail in U.S. Pat. No. 6,040,235 which is hereby incorporated by reference.
Each of the above-described technologies has certain limitations. Both wire bonding and TAB bonding are prone to bad bond formation and subject the die to relatively high temperatures and mechanical pressures. Additionally, wire bond and TAB technologies are problematic from a package size viewpoint, producing integrated circuit devices having a die-to-package area ratio ranging from about 10% to 60%.
The flip-chip technology actually refers to methods of interconnection rather than packaging methods. However, flip-chip interconnection suffers from a number of limitations. For example, variations in solder bump uniformity and thermal expansion mismatching present problems. These difficulties limit the use of available substrates to silicon materials or materials which have thermal expansion characteristics similar to those of silicon.
The “T-contact” method yields an interconnect structure that is extremely sensitive to process conditions and suffers from reliability problems associated with “T-contact” disassociation. These problems will be described in greater detail hereinbelow.
The difficulties of a known “T-contact” connection can be illustrated with respect to FIGS.
1
(
a
)-
1
(
d
). FIG.
1
(
a
) is a cross-section view depicting an edge portion of a semiconductor die
100
that has just been separated from a semiconductor wafer in a singulation process. A silicon substrate
101
having an integrated circuit formed on its surface has been sandwiched between two glass layers
102
,
103
. Also depicted are the backside solder balls
104
that are used to interconnect the die
100
to other electrical systems. These backside solder balls
104
are connected to front side electrical contact pads
105
by a specialized electrical connection called a “T-contact”. In this view, one such interconnection is shown by the metal layer
107
which makes electrical contact with one of the backside solder balls
104
.
FIG.
1
(
b
) is a close-up view depicting the “T-contact” electrical connection shown in the circular view
106
of FIG.
1
(
a
). The backside glass layer
103
affixed to the substrate
101
with a thin epoxy layer
113
. On the other side (the front side) of the silicon substrate
101
is a metal bonding pad
111
that is interconnected to the electronic circuitry formed on the silicon substrate
101
. Also, on top of the silicon substrate
101
is a first passivation layer
112
that is typically formed of SiO
2
. Some manufacturers add a second passivation layer
114
, formed of benzo-cyclo-butene (BCB), onto the first passivation layer
112
. The metal bonding pad
111
is accessible through an opening in the passivation layers
112
,
114
. Into the opening in the passivation layers
112
,
114
is deposited a metal plug
115
. Such plugs are commonly formed of Al—Si—Cu compounds (e.g., 94.5% Al, 5.0% Si, and 0.5% Cu). A tab
116
is typically formed over a portion of the passivating layers
112
,
114
as shown. The tab
116
portion includes an exposed facet
117
which has an exposed surface.
A top protective layer
102
is attached to the top surface of the substrate
101
using a thin layer of epoxy
118
. A metal layer
107
formed on the side of the die
100
forms an electrical contact with the exposed facet
117
thereby forming a conducting pathway to a corresponding solder ball (not shown) on the bottom of the die
100
. Commonly, the metal layer
107
is formed using a different material than the plug
115
and tab
116
materials. In one example, the metal layer
107
is constructed of a deposited layer of aluminum/copper (Al/Cu) material. Many other process steps are used to construct such structures. A full description of an example process for constructing such structures is included in the previously referenced U.S. Pat. No. 6,040,235.
Although suitable for some purposes, the aforementioned implementation has some serious drawbacks which will be described with respect to the simplified schematic illustrations of FIGS.
1
(
c
) and
1
(
d
). FIG.
1
(
c
) schematically depicts a simplified cross-section view of an intact “T-contact”. A metal layer
151
is shown in electrical contact with a tab
152
that is electrically connected to a bonding pad (e.g., as in FIG.
1
(
b
)). The connection between the metal layer
151
and the tab
152
is called a “T-contact”
153
. Under processing conditions, and also under some operating conditions the “T-contact”
153
can undergo significant stresses. Under some conditions, a separation can occur in the “T-contact”
153
causing electrical connection failure and consequently chip failure. This situation is schematically depicted in FIG.
1
(
d
), which shows a simplified cross-section view of an disconnected “T-contact”
154
. The interconnect metal layer
151
′ is shown with a break in electrical contact to the contact
152
′, thereby breaking the electrical connection to the bonding pad (not shown). The depicted “T-contacts” are very vulnerable to this kind of connection failure. Among the advantages of the disclosed invention is that it substantially reduces the aforementioned type of connection failure.
What is needed is a manufacturable robust electrical connection that does not suffer from “T-contact” failure. Also needed are methodologies for fabricating such structures. The principles of the present invention are directed toward an improved electrical connection and methodologies for its fabrication.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, the invention includes, among other things, a robust electrical connection and methods for its fabrication.
In one embodiment a semiconductor device having a plurality of edge mounted electrical contacts is disclosed. The embodiment includes an integrated circuit formed on a semiconductor substrate with first and second surfaces and edges. The first surface includes electrical contact pads electrically connected with the integrated circuit. The first surface of the semiconductor substrate includes a top protective layer that has a surface portion extending beyond the edges of the semiconductor substrate. The surface portion of the top protective layer includes electrical contact pads that are electrically connected with electrical contact pad extensions and with the integrated circuit. Th

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