Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2000-04-17
2002-05-07
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C257S048000
Reexamination Certificate
active
06383827
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a test structure and methodology for determining the alignment of layers formed on a semiconductor substrate. The present invention has particular applicability in manufacturing semiconductor devices having submicron features.
BACKGROUND ART
Semiconductor devices are conventionally manufactured by photolithographically forming a series of layers sequentially on a semiconductor substrate. For example, a patterned conductive polysilicon layer is typically formed to make electrical contact with active regions previously formed in the substrate, then a local interconnect (LI) is formed to selectively make electrical contact with the polysilicon layer. Subsequently formed conductive layers, such as patterned metal layers, typically make contact with previously formed layers directly or through conductive vias formed in interlayer insulating films. As semiconductor design rules continue to shrink, and the photolithographic process is pushed closer to its limits, in-process inspection of alignment between photolithographically formed layers is becoming increasingly critical.
A conventional method of inspecting the alignment between consecutively formed layers, such as two metal layers, involves forming a step or “box” in the first layer, then depositing the second layer, then determining by optical inspection where the photoresist image of the second layer is located relative to the first layer as indicated by the sidewall step coverage (i.e., determining the uniformity of the sidewall step coverage on the left and right sides of the step).
This optical inspection technique has several serious shortcomings. It allows analysis of the alignment of consecutively formed layers only, thus excluding alignment analysis of two layers having one or more layers in between them; for example, LI to active layer alignment. Moreover, optical inspection cannot be used for failure analysis. Time-consuming cross-sectioning of the wafer is required to inspect the alignment of layers other than the current layer and to conduct failure analysis. Thus, it is not practical to to test a large number of wafers using this methodology. Typically, only about two wafers are tested out of a lot, thereby reducing the statistical value of the inspection. Still further, the box structure used to test alignment does not replicate actual device structures. It is significantly larger than a typical device structure, and therefore photolithographically “prints” differently than actual device structures, resulting in undesirable inaccuracies that limit the optical test's utility as device structures become ever smaller.
To overcome the shortcomings of optical alignment tests, electrical test structures are conventionally employed, such as resistor divider type structures, as illustrated in FIG.
1
. Such test structures are usually conventional Kelvin or Van der Pauw resistors, and are typically formed at multiple sites on a wafer; e.g., about 120 sites including the corners and center of each die, to check the rotational alignment of the wafer and to check stepper performance. They enable electrical alignment tests to be conducted during processing on every wafer in a lot. The resistor divider structure of
FIG. 1
has an alignment-insensitive resistor
100
formed along with a first layer, such as polysilicon, and measuring points
110
,
120
at the center of resistor
100
formed along with a second layer, such as an LI layer. Probes are electrically connected at pads A-G. The ratio of the polysilicon resistance R1 to R2 multiplied by the drawn length of each yields the alignment offset in the x-direction. Likewise, R3/R4 times their drawn length yields the alignment in the y-direction.
The accuracy of resistor divider type alignment structures as shown in
FIG. 1
depends on the length of the resistor, the accuracy of the resistance measurement, and on design-process interactions. This type of test structure is more accurate with higher resistance films; however, resistance measurements are typically very small (i.e., fractions of an Ohm), thus limiting the accuracy of the test. The magnitude of this problem is increasing as devices are scaled and greater accuracy is required. Moreover, conventional test structures of this type require the two layers whose alignment is to be tested be in direct contact. Thus, as in optical inspection methods discussed above, only consecutive layers can be compared.
There exists a need for an electrical alignment test structure that enables every wafer to be quickly and accurately measured, and enables the alignment of non-consecutive layers to be checked.
SUMMARY OF THE INVENTION
An advantage of the present invention is an electrical alignment test structure that enables accurate alignment measurements at many sites on every wafer of a lot, and enables evaluation of the alignment of non-consecutive layers.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by an electrical test structure comprising a shorting bar of a first conductive layer disposed on a semiconductor substrate, the shorting bar having a base width, a top width less than the base width, and a pair of symmetrical opposing sides, each side comprising a predetermined number of steps and joining the base width and the top width; and a pair of ladder conductors of a second conductive layer disposed on the semiconductor substrate and aligned with the first conductive layer, the ladder conductors being symmetrical to each other about a center line, each ladder conductor comprising a plurality of serially connected segments arranged corresponding to the steps of the shorting bar, each segment having an inner end adjacent to one of the steps of the shorting bar, the inner ends of the segments being equidistant from the center line; wherein the shorting bar is disposed substantially between the ladder conductors; wherein the ladder conductors are spaced apart from each other such that when the first and second conductive layers are aligned in a predetermined manner, the shorting bar is substantially axially aligned with the center line, the inner end of a predetermined segment of one of the ladder conductors makes electrical contact with one of the steps on one side of the shorting bar, and a corresponding segment of the other ladder conductor makes electrical contact with a corresponding step on the opposing side of the shorting bar; and wherein the ladder conductors are spaced apart from each other such that when the shorting bar is not substantially axially aligned with the center line, the inner end of a predetermined segment of one of the ladder conductors makes electrical contact with one of the steps on one side of the shorting bar, and a corresponding segment of the other ladder conductor does not make electrical contact with a corresponding step on the opposing side of the shorting bar.
Another aspect of the present invention is a method of determining whether first and second conductive layers formed on a semiconductor substrate are aligned in a predetermined manner, the method comprising (a) forming the first layer to have a shorting bar, the shorting bar having a base width, a top width less than the base width, and a pair of symmetrical opposing sides, each side comprising a predetermined number of steps and joining the base width and the top width; (b) forming the second layer to have a pair of ladder conductors, the ladder conductors being symmetrical to each other about a center line, each ladder conductor comprising a pair of terminals and a plurality of serially connected segments between the terminals, the segme
Lukanc Todd
Selcuk Asim
Advanced Micro Devices , Inc.
Christianson Keith
Thompson Craig
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