Electric wiring forming method with use of embedding material

Details Electric wiring forming method with use of embedding material Electric wiring forming method with use of embedding material

1999-10-18

2001-11-20

Nguyen, Ha Tran (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S634000, C438S638000, C438S737000, C438S738000, C438S780000, C438S781000

Reexamination Certificate

active

06319815

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming an electric wiring structure with the use of an embedding material for use in filling up the via-holes thereof, in particular when forming a multi-layer wiring structure therewith.
2. Description of Prior Art
FIG. 1
shows a general method for forming a multi-layer wiring structure.
In the forming method of the multi-layer wiring structure according to the conventional art, first, as shown in FIG.
1
(
a
), a film of aluminum (Al) is formed on a substrate, and on the film a resist mask is prepared on which a pattern is formed. Then, as shown in FIG.
1
(
b
), the aluminum (Al) film is selectively etched by reactive ion etching (RIE) to remove the resist mask, thereby forming a lower layer of wiring. Next, as shown in FIG.
1
(
c
), SOG (i.e., spin on glass: a liquid dissolving silicon compound into organic solvent, such as alcohol, etc.) is applied and baked (though the SOG layer is provided directly on the Al wiring in FIG.
1
(
c
), an insulating layer may be provided between the layers of the Al wiring and the SOG layer through a plasma CVD method), and then, as shown in FIG.
1
(
d
), it is flattened by etching back. Further, as shown in FIG.
1
(
e
), the SOG is applied on the flattened surface and is baked, and the via-holes are formed by selectively etching on the SOG film through the resist mask prepared thereon, as shown in FIG.
1
(
f
). Into said via-holes, Al or the like is embedded or filled, and further, as shown in FIG.
1
(
g
), an aluminum (Al) film is formed and is etched so as to form an upper layer of wiring, in the same manner as in the above, as shown in FIG.
1
(
h
). Then, as shown in FIG.
1
(
i
), the SOG is applied for filling up between the upper layer wiring, thereby forming the multi-layer wiring structure.
However, most of the actual multi-layer wiring structures are made to five (5) layers or more, by applying the etching technology mentioned above.
The requirement for high integration of the semiconductor devices is continually rising, and now we are rushing into an age of 0.15 &mgr;m gate lengths. It is already recognized that, by using Cu as the wiring material in place of the conventional Al in such instances, improvements in the characteristics of the semiconductor elements produced can be obtained, in particular in the following aspects.
Cu is superior to Al in tolerance or durability to EM (i.e., electromigration), and is low resistance, therefore it is possible to reduce signal delay due to the wiring resistance, and use under high current density is possible, i.e., an allowable current density can be raised to three (3) times as large or more, thereby enabling fine or narrow wiring widths to be made.
However, since the etching of Cu is difficult compared to Al, a copper damascene method attracts attention as a method for realizing the multi-layer wiring of Cu without etching thereof.
Explanation of the copper damascene method will be given with reference to FIG.
2
.
First, as shown in FIG.
2
(
a
), an insulating film of SiO
2
or SOG is formed between the substrate and resist mask. It is formed on the substrate through a CVD method, and on the SiO
2
or SOG layer a resist mask is prepared. By selectively etching and removing the resist mask, wiring gutters are formed, as shown in FIG.
2
(
b
). Next, as shown in FIG.
2
(
c
), said wiring gutters are lined with barrier metal, and as shown in FIG.
2
(
d
), Cu is embedded or filled into the gutters by means of an electrolysis plating so as to form the lower layer wiring. After polishing the barrier metal and Cu with CMP (chemical mechanical polishing), and forming barrier metal thereon in addition, as shown in FIG.
2
(
e
), an insulating film between layers is then formed on the new layer. Hereinafter, in the same manner, by selectively etching the insulating film between layers through the resist mask on which a pattern is formed, as shown in FIG.
2
(
f
), the via-holes (or contact holes) and trench holes (i.e., the gutters for the upper layer wiring) are formed (i.e., dual damascene), and as shown in FIG.
2
(
g
), Cu is embedded or filled into the via-holes and the gutters for the upper layer wiring by means of electrolysis plating or the like, thereby forming the upper layer wiring.
The dual damascene method, for forming the via-holes and the trench holes in the insulating film between layers mentioned above, is disclosed for example in a monthly “Semiconductor World”, January, 1998, on pages 108 and 109, and the details thereof will be explained by referring to
FIGS. 3 and 4
, below.
In the method shown in
FIG. 3
, first of all, as shown in FIG.
3
(
a
), on the semiconductor substrate are formed a first low dielectric constant dielectric film, a first etching stopper film, a second low dielectric constant dielectric film and a second etching stopper film sequentially and respectively. Next, as shown in FIG.
3
(
b
), on the second etching stopper film a resist mask having a pattern for forming the via-holes is formed, and then, as shown in FIG.
3
(
c
), the via holes are formed through the resist mask to the bottom of the first low dielectric film constant dielectric. As shown in FIG.
3
(
d
), after filling an embedding material, such as a photo resist or the like into the via-holes and heating to harden, as shown in FIG.
3
(
e
), the embedding material being heated for hardening thereof is etched back so that a predetermined thickness of the embedding material remains on the bottom of each of the via-holes. Furthermore, as shown in FIG.
3
(
f
), a resist mask having a pattern for forming the trench holes therein is formed on the second etching stopper film, and then, as shown in FIG.
3
(
g
), the trench holes are formed in the second low dielectric film constant dielectric through the resist mask, while removing the remaining embedding material from the bottom of each of the via-holes, and thereafter, a metal such as Cu or the like is embedded or filled into the trench holes and the via-holes.
In the method shown in
FIG. 4
, first of all, as shown in FIG.
4
(
a
), on the semiconductor substrate are formed a low dielectric constant dielectric film and an etching stopper film sequentially, and then as shown in FIG.
4
(
b
), a resist mask having a pattern for forming via-holes is formed on the etching stopper film. Next, as shown in FIG.
4
(
c
), the via-holes are formed in the low dielectric constant dielectric film through the resist mask, and as shown in FIG.
4
(
d
), the embedding material, such as the photo resist is filled into the via-holes. After heating the embedding material for hardening thereof, as shown in FIG.
4
(
e
), said embedding material is etched back so that a predetermined thickness thereof remains on the bottom of each of the via-holes. Furthermore, as shown in FIG.
4
(
f
), a resist mask having a pattern for forming trench holes is formed on the etching stopper film, and as shown in FIG.
4
(
g
), the trench holes are formed in the low dielectric constant dielectric film through the resist mask, while removing the remaining embedding material from the bottom of each of the via-holes, and thereafter, metal is embedded or filled into the trench holes and the via-holes.
Further, there is known a dual damascene method other than the dual damascene method mentioned above, which does not make use of an embedding material such as the photo resist, and in which the trench holes are formed in advance, and then the via-holes are formed.
In the dual damascene method mentioned in the previous paragraph, when forming the trench holes through the etching after forming the via-holes, the surface of the substrate is damaged by the etching gas if it is exposed from the bottom of the via-holes. This causes defects in the wiring formed and so on. Therefore, the photo resist compound is embedded into the bottom of the via-holes as a protection film from said etching gas.
Sometimes, an aspect ratio (i.e., height/width) of the via-holes and the trench holes

Affiliated with

Also associated with

Rating

Electric wiring forming method with use of embedding material does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Electric wiring forming method with use of embedding material, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Electric wiring forming method with use of embedding material will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2616224