Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-03
2003-07-15
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S613000, C438S614000, C438S615000, C228S180220
Reexamination Certificate
active
06593220
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for bump electroplating using an elastomer mask.
(2) Description of the Prior Art
Semiconductor device performance improvements have since the inception of the semiconductor technology been achieved by reducing device and device feature dimensions, establishing shorter paths of electrical signal propagation. Device product improvements by device miniaturization have by necessity led to increasing device packaging density. Increased device density is typically implemented internally to the device, by creating device features of smaller dimensions. For devices that must be assembled into complete device packages, the completed semiconductor devices are frequently assembled in multi-device packages. This has led to the field of high density interconnect technology, mounting multilayer structures on the surface of a substrate and connecting integrated circuits to one another. This approach results in high wiring and high packaging density, whereby many integrated circuit chips are physically and electrically interconnected and connected to a single substrate commonly referred to as a multi-chip module (MCM). Electrical device isolation is provided by layers of dielectric, such as polyimide, that separate various functional planes (such as signal lines, power lines and ground planes) in a substrate. Metal interconnects can be provided by metal lines that are embedded in other layers of dielectric, using vias to provide electrical connections between the interconnect lines that are located in adjacent and overlying surfaces. Interconnect lines must thereby be connected in such a manner that optimum performance can be realized for the completed package. For instance, adjacent layers must be formed such that primary signal propagation directions are orthogonal to each other. This approach avoids crosstalk between closely spaced lines, which can induce false signals and noise between the adjacent lines. Good planarity must also be maintained between adjacent layers of interconnect lines. Metal interconnect lines are typically narrow in width and thick in a vertical direction (in the range of 5 to 10 microns thick) and must be patterned with microlithography. Patterned layers must therefore be substantially flat and smooth (i.e. have good planarity) so that these layers can serve as a base for overlying layers.
In making interconnections between sub-components of a semiconductor device, two types of interconnections can be distinguished. The connection that is made with the intent that this connection is relatively permanent and the connection that is making with the intent that this connection provides easy entry and removal of a component. As examples of the first method of interconnections serve solder joints and wire bond interconnects. The second type of interconnect can be exemplified by components that are inserted into a receptor socket from where these components can be readily removed. The receptor medium for such interconnects typically comprises tension loaded contact springs into which the contact pins of the guest component are inserted. One of the main considerations for both methods of establishing electrical contact between separate components is the number of pins (input/output pins or I/O count) that can be maintained in going from one package to the next. Maximizing the I/O count for these applications is a prime requirement, this driven by and to accommodate the previously mentioned increase in device packaging density.
One of the original approaches that has been used to create surface mounted, high pin count integrated circuit packages has been the use of Quad Flat Packs (QFP's) with various pin configurations. For QFP's, closely spaced leads along the four edges of the flat package are used for making electrical connections from where the electrical connections are distributed to the surrounding circuitry. The input/output connections that can be made to QFP packages are therefore confined to the edges of the flat package, which limits the number of I/O connections that can be made to the QFP even in applications where the pin to pin spacing is small. QFP's have found to be cost effective for semiconductor devices where the device I/O pin count does not exceed 200. To circumvent this limitation, a new package, a Ball Grid Array (BGA) package has been introduced. For the BGA package, the electrical contact points are distributed over the entire bottom surface of the package, eliminating the restriction of having I/O connects only around the periphery of the package. More contact points with greater spacing between the contact points can therefore be allocated across the BGA package than was the case with the QFP's. The contact points that are used for the BGA package are typically solder balls that have the added advantage of facilitating flow soldering of the package onto a printed circuit board.
A Ball Grid Array (BGA) is an array of solderable balls placed on a chip carrier, such as a Printed Circuit Board (PCB). The balls contact a printed circuit board in an array configuration where, after reheat, the balls connect the chip to the printed circuit board. BGA's are known with 40, 50 and 60 mil spacings in regular or staggered array patterns. The BGA package is part of a larger packaging approach that is often referred to as Chip Scale Packages (CSP), which is a packaging approach that is considered to be different from the previously highlighted approach of MCM's.
Flip Chip packages have in general been used to accommodate increased I/O count combined with increased requirements for high performance IC's. Flip chip technology fabricates bumps (typically Pb/Sn solder) on metal pads and interconnects the bumps directly to the package media, which are usually ceramic or plastic based. The flip-chip is bonded face down to the package through the shortest paths. This approach can be applied to single-chip packaging and to higher, integrated levels of packaging (in which the packages are larger) and to more sophisticated packaging media that accommodate several chips to form larger functional units.
For the packaging of semiconductor devices, the package in which the devices are contained provides protection of the device from environmental influences such as mechanical (surface) damage or damage caused by moisture or other chemical substances that may effect exposed surfaces of the device. Part of the package design includes the design of conductive interfaces that enable the device to be electrically interconnected with surrounding circuitry. Increased device density has not only created new demands on input/output connections of the device but has also caused considerably more energy (in the form of heat) to be expanded per cubic volume content of the device. This has resulted in increased demands placed on methods of heat exchange between the device and its surrounding and supporting surfaces. In many of the semiconductor device packages, the device is mounted in close physical proximity to a heat sink, which is often combined with providing paths of low thermal resistance between the device and the heatsink.
It is therefore the objective of providing a package for semiconductor devices, such as flip chips, that has a direct physical connection (contact) between the device and a substrate on the surface of which the device is mounted. In a typical device packaging arrangement, a substrate layer that contains multiple (for instance three) layers of interconnects, is used to connect the device to surrounding circuitry. Wire bond connections are made between the flip chip and the substrate layers. Contact points provided in or on the surface of the device make contact with contact points in the upper surface of the substrate layer, the substrate layer re-distributes (fan-out) the device electrical contact points. One of the approaches that have been used to create high t
Cheng Hsiu-Chieh
Chou Ken-Shen
Hsu Shun-Liang
Yu Hsiu-Mei
Ackerman Stephen B.
Chambliss Alonzo
Saile George O.
Taiwan Semiconductor Manufacturing Company
Talbott David L.
LandOfFree
Elastomer plating mask sealed wafer level package method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Elastomer plating mask sealed wafer level package method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Elastomer plating mask sealed wafer level package method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3033904