Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2006-12-12
2006-12-12
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S100000, C711S154000, C370S395700
Reexamination Certificate
active
07149842
ABSTRACT:
Broadly speaking, an apparatus for efficiently utilizing a shared packet buffer memory in a switch and a method for operating the same is provided. More specifically, the apparatus includes a memory having a number of buffers configured to be operated in a ratcheted manner. The ratcheted manner in which the memory is operated causes each incoming data stream to be distributed across the number of buffers. Each stored data stream can also be retrieved from the number of buffers for output from the memory in a similar ratcheted manner. The memory uses a rotating selector to control the ratcheted manner of operation. Also, the memory is capable of simultaneously servicing each of a number of inputs and a number of outputs to which the memory is connected.
REFERENCES:
patent: 6209056 (2001-03-01), Suh
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patent: 6493347 (2002-12-01), Sindhu et al.
patent: 6545934 (2003-04-01), Yamashita et al.
patent: 6891774 (2005-05-01), Abdollahi-Alibeik et al.
Chong, Jr. Fay
Lee Whay Sing
Nixon Walter
Martine & Penilla & Gencarella LLP
Sun Microsystems Inc.
Thai Tuan V.
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