Efficient utilization of a multi-source network of control...

Details Efficient utilization of a multi-source network of control... Efficient utilization of a multi-source network of control...

2011-07-12

2011-07-12

Lee, Thomas (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S400000, C713S401000, C713S500000, C713S501000, C713S502000, C713S503000, C713S601000, C716S113000, C716S114000

Reexamination Certificate

active

07979732

ABSTRACT:
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

REFERENCES:
patent: 6266803 (2001-07-01), Scherer et al.
patent: 6711716 (2004-03-01), Mueller et al.
patent: 2006/0190886 (2006-08-01), Lu et al.
patent: 2007/0286323 (2007-12-01), Shimobeppu

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