Efficient tile layout for a programmable logic device

Details Efficient tile layout for a programmable logic device Efficient tile layout for a programmable logic device

2007-05-22

2007-05-22

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

11152763

ABSTRACT:
In an integrated circuit including an array of substantially similar tiles, a tile includes a logic block and one or more columns of routing multiplexers driving interconnect lines that can be used to programmably interconnect the logic blocks. Each routing multiplexer in a first column drives a vertically adjacent subset of the routing multiplexers in the first and/or a second column. Optionally, each routing multiplexer also drives a vertically adjacent subset of a column of input multiplexers of a logic block. In some embodiments, the adjacent groups of routing multiplexers and input multiplexers driven by each routing multiplexer are horizontally aligned within the tile. In some embodiments, every signal coupled to drive one of the routing multiplexers in a column drives a vertically adjacent subset of the routing multiplexers. In some embodiments, each interconnect line has exit points, and every exit point drives a vertically adjacent set of the routing multiplexers.

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