Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-03-22
2005-03-22
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C324S765010
Reexamination Certificate
active
06871307
ABSTRACT:
A test system includes a test wafer having non-volatile memory dies and an exposed set of pads. A probe wafer includes test circuitry, a first set of pads exposed at a first surface, a second set of pads exposed at a second surface (opposite the first surface), and an interconnect structure. The interconnect structure includes traces that extend through the probe card or around the edges of the probe card, between the first and second surfaces. A prober aligns the test wafer with the probe wafer, such that the pads of the test wafer contact the first set of pads of the probe wafer. The prober further contacts the second set of pads of the probe wafer, and provides connections between these pads and a tester. The probe wafer is fabricated using semiconductor processing techniques, so that precise alignment exists between the test wafer and the probe wafer.
REFERENCES:
patent: 6127837 (2000-10-01), Yamamoto et al.
patent: 6133744 (2000-10-01), Yojima et al.
patent: 6380755 (2002-04-01), Sato
patent: 6525555 (2003-02-01), Khandros et al.
Bever Hoffman & Harms LLP
Hoffman E. Eric
Tower SemiconductorLtd.
Tu Christine T.
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