Efficient system bus architecture for memory and register...

Details Efficient system bus architecture for memory and register... Efficient system bus architecture for memory and register...

2000-07-11

2004-06-08

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S168000, C711S154000, C711S157000, C710S112000, C710S107000

Reexamination Certificate

active

06748505

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of The Invention
The present invention relates to a system bus used to perform data transactions within a processing system, and particularly to a system bus architecture used to perform memory and register transactions in a processing system.
2. State of The Art
A system bus in a processing or computing system is typically a shared communication link which uses one set of wires to communicate control, address, and data information between multiple sub-blocks within the processing system. The system bus uses a dedicated set of wires to perform the system communications, and often times different wires in the set are used to transmit different information. For instance, in some system buses, the same group of wires is used to transmit both data and addresses information. In this case, the data and address information is multiplexed onto the same system bus wires. In other system buses, data and address information is transmitted on physically separate groups of wires. In addition, different wires are often used to transmit control information such as bus request and grant signals or acknowledgment signals.
One of the sub-blocks that a system bus is connected to is the memory controller of the processing system which arbitrates and coordinates memory transactions on the system bus between the other systems sub-blocks as well as to an external memory.
FIG. 1A
shows a typical design of a system bus
11
in a processing system
10
having a processing unit
12
, a plurality of sub-blocks
13
, a memory controller
14
, and an external memory
15
(e.g., a disc drive or external memory device). As shown, the system bus includes a set of address lines, data lines, and control lines including request and grant lines.
FIG. 1B
shows a timing diagram illustrating a conventional data transfer between a sub-block
13
coupled to the system bus
11
and the external memory
15
. Initially, the sub-block transmits a request signal R
1
at time T
1
to the memory controller on a request signal line. The memory controller includes a means of arbitrating between requests on the system bus from the sub-blocks to determine which is to have control of the system bus to perform its memory transaction. Once, the memory controller arbitrator determines which sub-block's request is to be serviced next, it returns a grant signal G
1
at time T
2
to the sub-block. Upon the receipt of the grant signal, the sub-block begins transmitting an address A
1
at time T
3
to the memory controller for performing the read or write operation with the external memory. During this time the sub-block has control of the system bus and the remainder of the sub-blocks cannot transmit address or data information on it. Hence, only address A
1
is being transmitted on the address bus. The memory controller accesses the external memory with the address and at time T
4
begins transmitting data D
1
to the sub-block. Once the data is transmitted at time T
5
, the next request signal R
2
can be sent to the memory controller.
As can be seen in this timing diagram, due to latencies inherent to the system bus and the overall processing system architecture, both the address and data signal lines remain idle for many cycles while each memory request is being serviced. In particular, there is an associated latency that occurs from the time that the address A
1
is transmitted to the memory controller until the time that the data D
1
begins transmission which is caused by the inherent hardware (e.g., signal buffers, capacitive signal lines, drivers, flip-flops etc.) related delays of transmitting the signal through the sub-block, on the address signal line, through the memory controller, and then to the address pins of the external memory. In addition, there is a latency associated with arbitrating each memory transaction request which consists of several cycles for transmitting a request signal, for arbitrating the requests, and for transmitting the grant signal.
Moreover, traditionally, the system bus is used exclusively to perform memory transactions. Any other data transactions, such as a register transaction in which a register in one sub-block is read by or written to by, for instance, another sub-block or the system CPU, is performed using a completely separate bus system having its own arbitration and protocol scheme. As can be imagined, having a completely separate bus system for performing register transactions requires additional wiring and other circuitry to support the separate bus system resulting in an increased system size.
The present invention is a method of performing memory and register transactions on the system bus which 1) reduces the above described memory latencies, 2) minimizes the number of idle cycles of the address and data signal lines thereby increasing system bus efficiency, 3) can be used to perform register transactions thereby minimizing address and data signal line idle cycles, and 4) eliminates the need for a separate register transaction bus.
SUMMARY OF THE INVENTION
The present invention is a method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines.
In a first embodiment of the method for efficiently performing transactions on the system bus, a first memory transaction request is issued from a system sub-block to a memory controller on the request signal line and then granted by the memory controller. Upon the falling edge of the grant signal from the memory controller a second memory transaction can be issued after the grant of the first memory transaction—prior to the completion of the servicing of the first memory transaction. A first address corresponding to the first memory transaction request is then transmitted on the address signal lines of the system bus to the memory controller wherein the memory controller begins servicing the first memory transaction request. Once the first address is transmitted to the memory controller, the address lines are available for transmitting a second address corresponding to the second memory transaction request to the memory controller. The memory controller then stores the second address in a buffer whereupon the completion of servicing the first memory transaction request, the second request can be serviced without waiting for the address to be transmitted to the memory controller.
According to the first embodiment, more than one memory transaction request address can be buffered within the memory controller. Hence in this embodiment after the first memory transaction request is granted, arbitration occurs between any subsequent requests and a next request is granted depending on an arbitration technique. Once a next request is granted a corresponding address is transmitted to the memory controller and queued within the memory controller so that address and data are constantly being pumped through the address and data lines of the system bus with minimized idle cycles.
In a second embodiment of the method for efficiently performing transactions on the system bus, register transactions between system sub-blocks and the system's central processing unit are performed using the system bus by multiplexing register address and data signals onto the address signal lines of the system bus when the address signal lines are idle, thereby further minimizing address line idle cycles.


REFERENCES:
patent: 5006982 (1991-04-01), Ebersole et al.
patent: 6049847 (2000-04-01), Vogt et al.
patent: 6182176 (2001-01-01), Ziegler et al.
patent: 6442631 (2002-08-01), Neufeld et al.

Affiliated with

Also associated with

Rating

Efficient system bus architecture for memory and register... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient system bus architecture for memory and register..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient system bus architecture for memory and register... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3297509