Efficient source diffusion interconnect, MOS transistor and...

Details Efficient source diffusion interconnect, MOS transistor and... Efficient source diffusion interconnect, MOS transistor and...

2005-02-01

2005-02-01

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S369000, C257S382000

Reexamination Certificate

active

06849904

ABSTRACT:
Standard cell layout efficiency is improved by utilization of a MOS interconnect that minimizes features and geometries requiring compliance with space intensive design rules. Source diffusion regions of MOS structures have a substantially constant width extension extending toward a substrate pick-up diffusion and shares a common silicidation therewith to effect an ohmic contact thereto.

REFERENCES:
patent: 5654572 (1997-08-01), Kawase
patent: 5880503 (1999-03-01), Matsumoto et al.

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