Efficient sequential circuits using critical race control

Details Efficient sequential circuits using critical race control Efficient sequential circuits using critical race control

2001-09-05

2003-09-16

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S028000, C326S046000

Reexamination Certificate

active

06621302

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This present invention relates to integrated circuit design, and more particularly to synchronous and asynchronous sequential logic circuits and controlling critical races therein.
2. Background Art
Sequential logic circuits are heavily used in the implementation of very large scale integrated (VLSI) circuits. They appear as registers, as memory elements, as counters, in pseudo-random code generators and everywhere that data has to be manipulated such as in digital filters, data paths and logic operations. Therefore the improvement of such circuits such as a decrease in silicon area needed for implementation and/or a decrease in power consumption, without impairing other characteristics, is of prime importance to the VLSI industry. The resulting characteristics of the improved circuits would increase fabrication yield and/or increase the number of functions that can be implemented on the die.
Circuit size reduction also benefits conventional circuits that are too large or consume too much power to be efficiently used in VLSI circuits. For example, double edge-triggered D flip-flops (DETDFF) process data at both positive transition (low to high) and negative transition (high to low) of the clock. Compared to positive edge-triggered D flip-flop (PETDFF) which process data only at the positive transition of the clock, the DETDFF doubles the rate of data processing or, alternatively halves the clock rate thereby, either increasing the data throughput or reducing power consumption in the clock circuit respectively. However the implementation of conventional static DETDFF requires many gates and consumes too much silicon area to make them an attractive design alternative in VLSI circuits.
Sequential logic circuits are characterized by their structure that includes one or more feedback loops. The closed feedback loop “latches” or “stores” the present state of the circuit by closing the path returning the value of the circuit to its input. In synchronous sequential circuits, the opening and closing of the loop is controlled by a transition (low to high or high to low) of the clock waveform. The new value appears at the output node after a “propagation delay” due to the elements in the loop, and is held, or “memorized” by the loop until the signal to accept a new value appears.
The flip-flop is the basic synchronous sequential circuit. Flip-flops appear in various configurations or “types”, such as D flip-flops, T flip-flops and J-K flip-flops where the D flip-flop is the most common. Flip-flops, of all three types, are usually configured as Master-Slave flip-flops, i.e. a sequential structure using two latches, called master and slave respectively, in cascade. A latch is the simplest sequential circuit containing a single feedback loop for storing one bit of data.
In the case of a positive edge-triggered D flip-flop (PETDFF), a positive clock transition, or positive edge, determines the output of the flip-flop as that value present at its input just before the clock transition. Thus for correct operation the input value has to be maintained to a stable value just before and just after the clock transition.
The correct operation of flip-flops is dependent on the time delays internal to the feedback loops with respect to the external input and clock waveforms. Excessive delay in the feedback loop can result in faulty operation of the flip-flop. In the conventional use of sequential logic circuits, the time delay of feedback loops is usually a small fraction of the periods of input data and of clock waveforms and does not interfere with the correct operation of the circuit. Also in a well-designed sequential circuit, only one value is present at both ends of an open loop before the loop closes. At the appropriate closing time the loop will then latch that value.
However when more than one value is input to a feedback loop, a critical race develops between the conflicting values. The final value latched in the circuit as result of the critical race depends on the internal delay of the loop. The internal delay of a logic circuit loop, although generally small with respect to the periods of data and clock, is not well defined, as this delay is dependent on the parasitic elements in the loop. These parasitic elements are due to the non-linear input and output capacitances of the transistors, capacitive coupling with other elements, interconnection and load capacitances and finite resistance and inductance of wiring and switching transistors when being activated (in the “on” state).
One way to reduce the number of components in a master-slave flip-flop (M/S FF), and therefore reducing the required silicon area needed to implement it, consists of sharing a gate between the master latch and the slave latch. This eliminates one gate and its optional associated reset line. However sharing of the gate results in coupling between the feedback loops of the master and slave latches. This coupling between loops introduces critical races as the final state of the shared loop depends upon the value of which of the two latches will prevail and be the one to be latched. This critical race time interval is relatively small compared to the periods of clock and data, and is dependent upon the parasitic capacitances and resistances present in the coupled loop. The precise values of parasitic capacitances and resistances are unknown as they depend on the fabrication process. Thus, removing gates in the manner just described introduces critical races into the circuit, the final state of which is unknown.
This method, which introduces critical races, is therefore not practical or commercially viable. Accordingly, design practices for sequential logic circuits teach away from using critical race conditions in a circuit as this is assumed to create conditions that would make the circuit fail and/or generate unpredictable outcomes. Therefore present flip-flop configurations include additional circuitry to guarantee the absence of critical race conditions.
An additional way to avoid critical races is to have additional components to delay certain paths or to provide additional latching. However, as discussed herein, additional circuits increase power consumption and circuit area space.
In asynchronous sequential circuits critical races are also a problem, as no clock synchronization is used to close or open the feedback loop. In these circuits, as the feedback loop opens and closes under control of external signals unrelated to each other, more often than not more than one value is available instantaneously in the loop and critical races are often present.
Numerous approaches, such as unusual clocking and circuitry arrangements, have been used to eliminate race conditions and reduce circuit size. One example, U.S. Pat. No. 5,072,132, teaches a means of reducing circuit size by the use of a pulse generator coupled to the clock input of the latch. According to this design, a pulse generator produces sliver pulses correlating to the propagation delay through the latch of the state device circuits and thus purportedly enables a single latch to act as a flip-flop without racing. Alternatively, U.S. Pat. No. 4,841,168 teaches increasing circuit density by reducing gates, while avoiding racing. This is obtained by sharing a data gate between master and slave latches such that a latch gate of the master latch is shared by the slave latch as a data gate. Additionally, the clock signal is altered by changing the signal transmission speed of the clock on the slave side of the gate and adding control signals to the clock driver.
Additional background information on critical races can be found in “Fundamentals of Logic Design”, by Charles H. Roth, Jr., West Publishing Company, 1992, Ch. 23, p. 602-603 and Ch. 25, p.629. Operation of a static double edge-triggered flip-flop is detailed in the paper: “High-performance two-phase micropipeline building blocks: double edge triggered latches and burst mode select and toggle circuits” by Yun, K. Y., Beerel, P. A. and Arce

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