Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-27
2001-07-31
Smith, Matthew S. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C326S038000, C326S041000
Reexamination Certificate
active
06269470
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuit routing. More particularly, the present invention provides a method for routing conductors between datapaths which minimizes the number of tracks required to connect the datapaths.
2. The Background Art
Modem integrated circuit designs often include common blocks of circuitry which are organized so that each block operates on a single bit of data. A group of these blocks is called a datapath. It is typical to have several datapaths linked together in order to perform complex desired logical functions on binary data.
FIG. 1
is a diagram showing two datapaths which are to be connected.
Referring to
FIG. 1
, datapath
10
includes N blocks of functional circuitry. Each block of circuitry is identical for a given datapath, but each datapath is most often different from each other datapath. Datapath
12
also includes N blocks of functional circuitry which may be the same or different as the functional circuitry included in the blocks making up datapath
10
.
It is typical that each block in one datapath is designed to couple to a corresponding block in a second datapath. For example, the outputs of blocks
14
and
16
of datapath
10
would be designed to be connected to the inputs of block
18
and
20
of datapath
12
respectively, proceeding in the same manner for all blocks in each datapath until the inputs of all blocks in the first datapath are coupled to the corresponding output in the respective blocks in the other datapath.
FIG. 2
illustrates portions of two datapaths coupled together using horizontal and vertical tracks.
Shown in
FIG. 2
are portions of datapaths
30
and
32
coupled together using conductive paths
34
,
36
,
38
, and
40
. Each conductive path has two vertical portions called vertical tracks, and one horizontal track. Each dotted line
42
a
through
42
h
is a horizontal location which can hold a horizontal track portion of a one or more conductive paths.
Vertical portions of conductive paths are typically placed on layers of a multilayer integrated circuit different than those layers containing the horizontal portions of conductive paths. Thus, conductive paths
38
and
40
are electrically distinct.
Those of ordinary skill in the art are readily aware that the placement of conductive paths which connect blocks on different datapaths together are routed by software routines within a program typically called a router. A router typically is given the coordinates of the endpoints of a desired conductive path and then routes the metal layers which include the horizontal and vertical tracks so that the endpoints are connected.
In the prior art, conductive lines are routed somewhat randomly. That is, path
36
may or may not be routed prior to conductive paths
34
or
38
. this randomness usually results in more horizontal track locations being required than are necessary to accomplish the routing of all conductive paths. Using more than the minimum number of tracks causes valuable space to be used which could otherwise be used for a different purpose.
It would therefore be beneficial to provide a systematic method for routing conductive paths between datapaths which is efficient and utilizes only the minimum number of horizontal track locations required.
SUMMARY OF THE INVENTION
A method for routing N conductive paths between a first datapath and a second datapath in an integrated circuit is described. The method includes determining the degree of alignment between block one from the first datapath to block one from the second datapath, and determining the degree of alignment between block N from the first datapath to block N from the second datapath. Following the determination of the degree of alignment, the least aligned block pair to be routed is chosen from block one and block N. Next, a first horizontal track location to be used for routing the desired connection between said first datapath and said second datapath is chosen, and the corresponding conductive path is then routed using that track location. For each of the remaining unrouted block pairs, the next block pair to be routed is chosen to be the unrouted block pair immediately adjacent to the most recently routed block pair. It is then determined whether the desired conductive path may successfully be routed using a previously defined track location, and if so, using that location for the routing. If not, a new track location is defined and used to route the desired conductive path.
REFERENCES:
patent: 5850348 (1998-12-01), Berman
patent: 5896300 (1999-04-01), Raghavan et al.
patent: 6163475 (2000-12-01), Proebsting
patent: 6218855 (2001-04-01), Ghosh et al.
Hou, et al., “A hierarchical methodology to improve channel routing by pin permutation”; IEEE International Conference on Computer-Aided Design; 1991, pp. 440-443.*
Lin, et al., “Maximum alignment of interchangeable terminals”; IEEE Transactions on Computers; vol. 37 10, Oct. 1988; pp. 1166-1177.
Sierra Patent Group Ltd.
Smith Matthew S.
Speight Jibreel
Sun Microsystems Inc.
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