Electronic digital logic circuitry – Multifunctional or programmable – Array
Utility Patent
1998-06-24
2001-01-02
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S041000, C326S039000, C326S040000, C326S101000, C327S565000, C365S063000
Utility Patent
active
06169418
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention pertains to a system and method for routing signals between a plurality of devices and one or more circuit blocks on an integrated circuit (IC) chip using minimal space on the IC chip.
2. Description of the Related Art
IC chips frequently contain one or more circuit blocks which must be suitably coupled to a plurality of devices for the IC chip to operate properly. This typically is accomplished using pluralities of conductive lines. Because these conductive lines require space on the IC chip, the circuit blocks and devices are spaced apart from one another on the IC chip, and the conductive lines are routed through the spaces between the circuit blocks and devices.
In many instances, multiple layers of conductive lines suitably insulated from one another can be fabricated over circuitry to achieve sufficient routing space. For example, such conductive lines can be formed from one or more layers of metal or polysilicon, with the various layers being insulated from one another using one or more layers of silicon dioxide. Complex IC chips frequently have four or more layers of these conductive lines. However, very little or no additional routing can occur over some types of circuit blocks due to noise issues or because space over the circuit block must be fully reserved for the circuit block itself. This makes routing signals to the circuit block difficult because there is much congestion or blockage in its vicinity.
Referring now to
FIG. 1
, there is shown a block diagram illustrating a conventional system
100
for interconnecting several electrical devices on an IC chip
90
to a single terminal
51
of a circuit block
50
on the IC chip
90
. These electrical devices include pads
10
,
60
, a logic block
20
, and a built in self test (BIST) unit
30
. The IC chip
90
also includes a multiplexor
40
and a plurality of conductive lines
14
,
24
,
34
,
44
,
22
, and
62
. Pad
10
is coupled by conductive line
14
to a first data input of the multiplexor
40
, the logic block
20
is coupled by conductive line
22
to a second data input of the multiplexor
40
, and the BIST unit
30
is coupled by conductive line
34
to a third data input of the multiplexor
40
. The logic block
20
is further coupled by conductive line
24
to a first selection input of the multiplexor
40
, and pad
60
is coupled by conductive line
62
to a second selection input of the multiplexor
40
. The output of the multiplexer
40
is coupled to terminal
51
of the circuit block
50
.
In operation, the logic block
20
and pad
60
supply control signals to the election inputs of the multiplexor
40
. If the first data input is selected, then signals from the pad
10
will be asserted by the output of the multiplexor
40
via conductive line
44
onto terminal
51
of the circuit block
50
. Similarly, if the third data input is selected, then the signal from the BIST unit
30
will be asserted by the output of the multiplexor
40
via conductive line
44
onto the terminal
51
of the circuit block
50
.
Conventional system
100
is limited. Each of these lines
14
,
24
,
34
occupies space on the IC chip
90
which reduces the amount of circuitry which can be fabricated on the IC chip
90
. Additional metal layers may be needed to form the various lines
14
,
24
,
34
. Further, two conductive lines
22
,
62
are required to provide control signals to the multiplexor
40
. These two lines
22
,
62
also occupy space on the IC chip
90
. To reduce the total length of conductive line employed in routing the circuit block
50
, the multiplexor
40
typically is located in the vicinity of the circuit block
50
. However, this also increases routing congestion in the vicinity of the circuit block
50
. Conventional system
100
thus requires significant space on the IC chip
90
to implement, and performs increasingly poorly as the number of terminals of circuit block
50
is increased. Further, the paths shown in
FIG. 1
are unidirectional, and circuit block
50
cannot therefore supply signals to the pad
10
, logic block
20
, and BIST unit
30
in conventional system
100
.
Referring now also to
FIG. 2
there is shown a block diagram illustrating a second conventional system
200
for interconnecting several electrical devices to circuit block
50
on IC chip
90
. In conventional system
200
, circuit block
50
includes an additional terminal
52
through which the circuit block
50
receives signals from the logic block
20
, BIST unit
30
, and an additional pad
110
. Pad
10
, logic block
20
and BIST unit
30
are coupled by lines
14
,
24
,
134
, multiplexor
40
, and conductive line
44
to terminal
51
of circuit block
50
as in conventional system
100
. Additional pad
110
is coupled by a first additional conductive line
114
to a first data input of an additional multiplexor
140
. The logic block
20
is further coupled by a second additional conductive line
26
to a second data input of the multiplexor
140
. The BIST unit
30
is coupled by a third additional conductive line
36
to a third data input of the multiplexor
140
. The multiplexor
140
also has selection inputs which are coupled to lines
162
and
122
for receiving control signals from pad
60
and logic block
20
.
In operation, the logic block
20
and pad
60
supply control signals respectively via lines
122
,
162
to the selection inputs of multiplexors
40
and
140
. The first data input of each multiplexor
40
,
140
is enabled at the same time, and similarly for the second and third data input of each multiplexor
40
,
140
. If the first data inputs are enabled, then pad
10
communicates via conductive line
14
, multiplexor
40
, conductive line
44
, and terminal
51
with the circuit block
50
; and similarly, pad
110
communicates via conductive line
114
, multiplexor
140
, conductive line
144
, and terminal
52
with the circuit block
50
. The logic block
20
and BIST unit
30
communicate with the circuit block
50
in similar manner.
Conventional system
200
is highly limited. First, lines
122
,
162
require more space on the IC chip
90
to implement than corresponding lines
22
,
62
of conventional system
100
because lines
122
,
162
provide signals to two different destinations, whereas the corresponding lines
22
,
62
each provide signals to a single destination. Due to routing requirements, conductive line
134
is significantly longer than corresponding conductive line
34
of conventional system
100
, and hence requires significantly more space on the IC chip
90
to implement. Lines
114
,
26
,
36
and dual destination lines
122
,
162
are occupying portions of the space on the IC chip
90
where conductive line
34
is routed in FIG.
1
. Thus, as the number of terminals of the circuit block
50
is increased, the conventional system
200
typically requires much more space to implement. Another significant limitation with conventional system
200
is caused by the additional multiplexor
140
. This multiplexor
140
occupies space on the IC chip
90
. Like multiplexor
40
, multiplexor
140
typically is located in the vicinity of the circuit block
50
, which obstructs access to the circuit block
50
, and makes routing of the various conductive lines
14
,
24
,
134
,
114
,
26
,
36
,
122
,
162
much more space intensive.
These various limitations with conventional system
200
become increasingly significant as the number of terminals of the circuit block
50
is increased. This is a very important problem in current IC chip designs. For example, over the last few years it has become increasingly valuable to include both a large dynamic random access memory (DRAM) unit and a processing unit on the same IC chip. This greatly reduces the time required to obtain information from DRAM compared to locating DRAM and processing units on separate IC chips. However, large DRAM units typically have a very large number of terminals. A two megabyte DRAM unit would t
Fenwick & West LLP
S3 Incorporated
Tan Vibol
Tokar Michael
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