Efficient reduction of read disturb errors in NAND FLASH memory

Details Efficient reduction of read disturb errors in NAND FLASH memory Efficient reduction of read disturb errors in NAND FLASH memory

2009-09-24

2010-10-19

Bragdon, Reginald G (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C711S103000, C711SE12001, C365S185250

Reexamination Certificate

active

07818525

ABSTRACT:
Methods and apparatuses for reduction of Read Disturb errors in a NAND FLASH memory system comprise a controller configured to organize FLASH memory devices into blocks, each block having a plurality of pages, and each page defining an individually addressable physical memory location. The controller is further configured to accumulate a Block READ Count corresponding to the number of times any pages in a first block of pages have been read since the first block was last erased. Once the READ count reaches a predetermined number, the controller responds to subsequent READ requests for pages within the first block by moving data associated with a requested page to a page in a second, different block without moving data associated with other pages in the first block, and modifying a logical-to-physical translation table to associate the moved data with the physical address of the page in the second block.

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