Efficient provision of alignment marks on semiconductor wafer

Details Efficient provision of alignment marks on semiconductor wafer Efficient provision of alignment marks on semiconductor wafer

2010-02-10

2011-10-25

Parker, Kenneth (Department: 2815)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Having substrate registration feature

C438S462000, C257S797000, C257SE23179

Reexamination Certificate

active

08043928

ABSTRACT:
A semiconductor wafer includes multi chip areas each including two or more device chip areas and arranged in an X-axis direction and a Y-axis direction, a plurality of scribe lines formed parallel to the X axis and the Y axis such as to separate the device chip areas from each other, and one or more alignment marks formed in each of the multi chip areas on the scribe lines between adjacent ones of the device chip areas included in one multi chip area, the one or more alignment marks being fewer than the device chip areas in each of the multi chip areas and used for positioning of the semiconductor wafer.

REFERENCES:
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patent: 2002-237446 (2002-08-01), None
patent: 2005-44838 (2005-02-01), None

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