Efficient processing of data requests with the aid of a...

Details Efficient processing of data requests with the aid of a... Efficient processing of data requests with the aid of a...

2008-07-07

2011-11-08

Yu, Jae (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S119000, C711S141000, C711S151000, C711S158000

Reexamination Certificate

active

08055847

ABSTRACT:
A method and system for configuring a cache memory system in order to efficiently process processor requests. A group of cache elements, which include a Region Cache, a Region Coherence Array, and a lowest level cache, is configured based on a tradeoff of latency and power consumption requirements. A selected cache configuration differs from other feasible configurations in the order in which cache elements are accessed relative to each other. The Region Cache is employed in a number of configurations to reduce the power consumption, latency, and bandwidth requirements of the Region Coherence Array. The Region Cache is accessed by processor requests before (or in parallel with) the larger Region Coherence Array, providing the region coherence state and power efficiently to requests that hit in the Region Cache.

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Gupta, A et al., Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes, Proceedings of the International Conference on ParallelProcessing, Aug. 13, 1990, pp. I312-I321.

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