Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-03-27
2001-04-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S014000
Reexamination Certificate
active
06212665
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to power evaluation of an electronic circuit design. More particularly, the present invention relates to a power evaluation system and a power evaluation tool that use simple arcs for calculating the power dissipation of an electronic circuit design under simulation.
2. Background
Power evaluation of integrated circuits (ICs), such as calculating on-chip power dissipation of logic circuits, has become more important, in part, due to the growing number of mobile products and the need to determine “hot spots” on ICs early in the design stage. Also, power evaluation has become much more complex since the increases in die size, speed (even though feature size and/or voltage supply may decrease), and device count of ICs has greatly complicated the task of optimizing power dissipation.
The ability to accurately evaluate, predict, and optimize power dissipation of an IC, or cells within the IC, enables designers to design better products. Power dissipation is a major issue in mobile products by virtue of the battery driven nature of such products, with lower power consumption resulting in longer battery life per charge. Low power dissipation also means lower package and die costs. In high performance computer products, power dissipation is a major concern since excessive power consumption, either by heat or by electro-migration, can damage a chip. Thus, there has been an increase in the reliance and use of power analysis tools to aid in the fabrication of ICs using traditional fabrication design tools.
The term EDA (Electronic Design Automation) as used herein includes all design automation tools that facilitate the design of an electronic circuit at the behavior, register, gate-level transistor and/or layout levels.
Also, the term cell is intended to include circuit portions within an IC that can be identified as discrete structures providing a function. For example, depending on the level of abstraction used to model a cell, the term may include structures defined at the physical level such as a transistor; at the gate/logic level such as a NAND or OR gate; or at the macro level such as a simple adder or flip-flop. The level of abstraction used depends on the design cycle stage and the speed at which modeling needs to be completed, among other things. Design automation tools that generate cell models at higher levels of abstraction tend to run faster but have a relatively greater margin of error, while such models using lower levels of abstraction tend to run slower but have a relatively lower margin of error.
Power dissipation within a cell has two fundamental components—dynamic and static power dissipation. Dynamic power dissipation is the amount of power expended by a cell in response to at least one input signal transitioning from one switching threshold to another (input signal transition) and which may also result in at least one output signal transition from one switching threshold to another within a given time period. For example, an input signal going from high to low, or vice versa, is defined as an input signal transition. Static power dissipation is the power dissipated due to current flowing from Vdd to ground such as when no signals are switching from one logic state or another. Thus, dynamic power dissipation is a function of circuit switching activity and the state of the cell, while static power dissipation is only a function of the logic state of the circuit.
The focus of the following invention is on dynamic power dissipation rather than static power dissipation since dynamic power dissipation represents a much larger portion of the total power dissipation of a typical logic circuit.
Dynamic power dissipation comprises a charge/discharge power component due to capacitive load and a short-circuit power component due to the effect of non-ideal switches that cannot be turned on and off instantaneously. As discussed in “On-Chip Power Evaluation Methods and Issues,” by authors Amir Zarkesh and Wolfgang Roethig, published in the proceedings of the session entitled “On-chip Systems Design Conference,” Design Supercon 97, page S141-S141-33, ISDN: 0-1933217-29-3,the energy dissipated for a charge of capacitance can be expressed with the equation below, where E is the total energy dissipated for a given capacitance C and voltage Vdd.
E=
½*
C*Vdd
Therefore, the charge/discharge power consumed by a driver of a signal switching circuit with frequency f is:
P=f*[
½*
C*Vdd].
For circuits that do not switch at a constant frequency f, an effective frequency, f_eff may be introduced. The effective frequency is the basic switching frequency multiplied with an activity factor, act, and is shown by the following equation: f_eff=f* act.
Table 1 below shows the activity factors for certain types of cell activities.
TABLE 1
Signal
Activity Factor
Clock
2
Counter LSB
1
Random Data
0.5
Reset
Approx. 0
FIG. 1
is a schematic diagram showing a capacitive output load seen by the output pin of a driving cell in an example electronic circuit. For example, the capacitive output load seen by an output pin
2
at driving cell
4
includes cell load
6
and wire load
8
. Cell load
6
includes all input pin capacitances of cells driven by driving cell
4
, such as input pin capacitances
10
a
through
10
n
in cells
12
a
through
12
n
, respectively. Wire load
8
is the sum of the effective capacitance of net
14
to which output pin
2
is attached.
Measuring the cell load of driven cells may be accomplished through design automation modeling. Wire load may be measured through parasitic extraction if the wire load is calculated at the post-layout state. Parasitic extraction is known in the art. Both self capacitance to Vdd and Vss, and mutual capacitance to other signal interconnect wires also must be taken into account when measuring wire load.
Short-circuit power is proportional to the effective frequency f_eff since short circuit power always occurs concurrently with dynamic power and is dependent on the short circuit current path of a cell. As known in the art, characterization by accurate simulation is one method of modeling short circuit power in a cell.
Analyzing the power dissipation in an electronic circuit having multiple and/or different structures or cells, requires differentiating between external and internal cell power dissipation. External power may be defined as the power dissipated due to an external load, while internal power consists of short circuit power plus charge/discharge power dissipated by internal cell capacitances. Thus, in an electronic circuit having multiple cells or stages, both charge/discharge power and short circuit power in every cell must be calculated to determine the total power dissipation of the circuit. Since short circuit power of internal states of a cell depends on internal input slew rates rather than on primary input slew rates, and since the capacitive load is only seen by the last stage, the slew rate and load dependency of internal power is somewhat decoupled. The first stage is affected by the input slew rate (its load is a constant internal capacitance), and the last stage is affected by the external load seen by the last stage (since the last stage's input slew rate is an internal slew rate weakly affected by the primary input slew rate).
As known in the art, the term “slew rate” is defined as the rate of change of a voltage signal that changes from one signal value to another signal value over-time, such as a logic transition that changes from a logic LOW state to a logic HIGH state, or vice versa.
Power dissipation in sequential cells, such as a basic latch or flip-flop, is discussed below. A basic latch consumes power, if an input switches while the latch is transparent. If the latch is blocked, the switching input causes no power consumption. A flip-flop consists of basic master and slave latches in addition to an input buffer and a clock buffer. Therefore, power is consumed whenever the input or
Chen Haizhou
Zarkesh Amir M.
Do Thuan
Ritchie David B.
Smith Matthew
Synopsys Inc.
Thelen Reid & Priest LLP
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