Efficient pMOS ESD protection circuit

Details Efficient pMOS ESD protection circuit Efficient pMOS ESD protection circuit

2005-11-08

2005-11-08

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S357000, C257S358000, C257S359000, C257S360000, C257S361000, C257S362000, C257S363000, C257S364000, C257S365000

Reexamination Certificate

active

06963111

ABSTRACT:
A pMOS transistor (601) is located in an n-well (602) and has at least one gate (603). Transistor (601) is connected between power pad Vdd or I/O pad (604) and ground potential Vss (605). Gate (603) is connected to power pad (604). The n-well (602) is capacitively (620) coupled to ground (605), decoupled from the transistor source (606) and floating under normal operating conditions. Under an ESD event, the diode formed by the source (606) and the n-well (602) is forward biased (n-well negatively biased) to turn on the lateral pnp transistor to discharge the ESD current. The well voltage keeps increasing up to the value that triggers the lateral bipolar pnp transistor. The ESD protection is scalable with the width of gate (603), improving with shrinking gate width.

REFERENCES:
patent: 4821096 (1989-04-01), Maloney
patent: 6455897 (2002-09-01), Okawa et al.
patent: 6529035 (2003-03-01), Schroeder et al.
patent: 2003/0048588 (2003-03-01), Duvvury et al.
patent: 2003/0076645 (2003-04-01), Ker et al.

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