Efficient on-chip instruction and data caching for chip...

Details Efficient on-chip instruction and data caching for chip... Efficient on-chip instruction and data caching for chip...

2006-06-20

2009-06-02

Tsai, Sheng-Jen (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

Reexamination Certificate

active

07543112

ABSTRACT:
The storage of data line in one or more L1 caches and/or a shared L2 cache of a chip multiprocessor is dynamically optimized based on the sharing of the data line. In one embodiment, an enhanced L2 cache directory entry associated with the data line is generated in an L2 cache directory of the shared L2 cache. The enhanced L2 cache directory entry includes a cache mask indicating a storage state of the data line in the one or more L1 caches and the shared L2 cache. In some embodiments, where the data line is stored in the shared L2 cache only, a portion of the cache mask indicates a storage history of the data line in the one or more L2 caches.

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U.S. Appl. No. 11/654,150, filed Jan. 16, 2007, Spracklen et al., entitled “Efficient Caching of Stores in Scalable Chip Multi-Threaded Systems”.

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