Efficient on-chip accelerator interfaces to reduce software...

Details Efficient on-chip accelerator interfaces to reduce software... Efficient on-chip accelerator interfaces to reduce software...

2007-03-09

2010-11-02

Thomas, Shane M (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Operand address generation

C711S001000, C711S203000, C711SE12058, C710S004000, C712S034000

Reexamination Certificate

active

07827383

ABSTRACT:
In one embodiment, a processor comprises execution circuitry and a translation lookaside buffer (TLB) coupled to the execution circuitry. The execution circuitry is configured to execute a store instruction having a data operand; and the execution circuitry is configured to generate a virtual address as part of executing the store instruction. The TLB is coupled to receive the virtual address and configured to translate the virtual address to a first physical address. Additionally, the TLB is coupled to receive the data operand and to translate the data operand to a second physical address. A hardware accelerator is also contemplated in various embodiments, as is a processor coupled to the hardware accelerator, a method, and a computer readable medium storing instruction which, when executed, implement a portion of the method.

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