Efficient NPN turn-on in a high voltage DENMOS transistor for ES

Details Efficient NPN turn-on in a high voltage DENMOS transistor for ES Efficient NPN turn-on in a high voltage DENMOS transistor for ES

1999-02-16

2000-10-31

Dutton, Brian

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257363, H01L 2362

Patent

active

06140683&

ABSTRACT:
A high voltage DENMOS transistor (10) having improved ESD protection. The transistor (10) is optimized to provide maximum substrate current in order to turn on the inherent lateral npn transistor during an ESD event so that the lateral npn can dissipate the ESD event without damage to the transistor (10). This is accomplished by optimizing the overlap (A) of the drain extended region (16) and the gate electrode (28) to control the gate coupling to achieve maximum substrate current.

REFERENCES:
patent: 5173755 (1992-12-01), Co et al.
patent: 5369041 (1994-11-01), Duvvury
patent: 5453384 (1995-09-01), Chatterjee
patent: 5907462 (1999-05-01), Chaterjee

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