Efficient memory management for channel drivers in next...

Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring

Reexamination Certificate

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Details

C711S150000

Reexamination Certificate

active

06421769

ABSTRACT:

BACKGROUND
The present invention relates to efficient memory management for channel drivers in Next Generation I/O systems.
Most server systems today use a shared-bus, memory-mapped method to link peripheral controller devices. By far the most widely used system bus is the Peripheral Component Interconnect (PCI) bus. The PCI bus was developed originally for use in PCs, but server manufacturers have broadly and successfully deployed PCI buses in server systems.
However, the widespread deployment of “I/O-centric” Internet applications for Web servers, e-commerce, Transmission Control Protocol/Internet Protocol (TCP/IP) networking, mail services, and on-line transaction processing is now creating demands on server Input/Output (I/O) subsystems that the PCI bus is not able to address. Those demands relate primarily to the reliability and scalability of the connection between server memory and I/O peripheral controller devices.
Next Generation I/O (NGIO) is an I/O architecture that was designed to meet the demands of the Internet and mission-critical e-commerce applications. NGIO is a new technology designed to address the reliability and scalability needs of mission-critical platforms of all kinds.
SUMMARY
An efficient memory management system for managing channel drivers is desired. The memory management system includes a plurality of memory elements to enable translation of virtual memory addresses to physical memory locations. The memory elements have at least first and second memory element configurations. The first and second memory element configurations separately process allocated memory elements and unused memory elements, respectively.


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