Efficient memory controller

Details Efficient memory controller Efficient memory controller

2008-05-06

2008-05-06

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S151000, C710S006000

Reexamination Certificate

active

07370169

ABSTRACT:
An efficient memory controller. The controller includes a first mechanism for associating one or more input command sequences with one or more corresponding values. A second mechanism selectively sequences one of the one or more command sequences to a memory in response to a signal. A third mechanism compares each of the one or more values to a state of the second mechanism and provides the signal in response thereto. In a specific embodiment, the one or more corresponding values are execution time code values, and the second mechanism includes a sequencer state machine that provides the state of the second mechanism as a sequencer time code. In the specific embodiment, a compare module compares the sequencer time code to a time code associated with a next available command sequence and execution time code pair and provides the signal in response thereto.

REFERENCES:
patent: 5890193 (1999-03-01), Chevallier
patent: 6212611 (2001-04-01), Nizar
patent: 6219769 (2001-04-01), Strongin
patent: 6304923 (2001-10-01), Klein
patent: 6532505 (2003-03-01), Stracovsky et al.
patent: 6587894 (2003-07-01), Stracovsky et al.
patent: 7010654 (2006-03-01), Blackmon et al.

Affiliated with

Also associated with

Rating

Efficient memory controller does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient memory controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient memory controller will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2814489