Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-01-16
2007-01-16
Lane, Jack A. (Department: 2185)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S046000, C717S124000, C717S128000
Reexamination Certificate
active
10972622
ABSTRACT:
A system and method that provides an integrated circuit which includes a small on-chip buffer to store collected data, thereby shifting the burden of storing the majority of the collected data to external system memory, which is typically comprised of commodity memory chips. Since this external system memory is already in use by other system functions, utilizing such unused regions of this external memory increases overall hardware efficiency, while achieving lower ASIC manufacturing cost.
REFERENCES:
patent: 5560036 (1996-09-01), Yoshida
patent: 5768152 (1998-06-01), Battaline et al.
patent: 0 316 609 (1989-05-01), None
Chen Joey Y.
Hebsgaard Anders
Lin Thuji Simon
Mote L. Randall
Broadcom Corporation
Lane Jack A.
Sterne Kessler Goldstein & Fox PLLC
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