Efficient marking of shared cache lines

Details Efficient marking of shared cache lines Efficient marking of shared cache lines

2006-12-06

2009-06-16

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S144000

Reexamination Certificate

active

07549025

ABSTRACT:
One embodiment of the present invention provides a system that efficiently marks cache lines in a multi-processor computer system. The system starts by receiving a load request for a cache line from a requesting thread. Upon receiving the load request, the system loads a copy of the cache line into a local cache for the requesting thread. The system then load-marks the copy of the cache line in the local cache by incrementing a reader count value contained in metadata for the copy of the cache line, regardless of the cache coherency protocol status of the copy of the cache line, whereby the system updates the metadata in the local copy of the cache line without obtaining exclusive access to the cache line.

REFERENCES:
patent: 2004/0187123 (2004-09-01), Tremblay et al.
Anant Agrawal et al., “ATUM: A New Technique for Capturing Adress Traces Using Microcode”, Proceedings of 13th Annual International Symposium on Computer Architecture, 1986, pp. 119-127.
Publication: “Token Coherence: A New Framework for Shared-Memory Multiprocessors” by Milo M.K. Martin et al., IEEE Computer Society, Nov.-Dec. 2006, pp. 108-116.

Affiliated with

Also associated with

Rating

Efficient marking of shared cache lines does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient marking of shared cache lines, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient marking of shared cache lines will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4065693