Efficient loadable registers in programmable logic devices

Details Efficient loadable registers in programmable logic devices Efficient loadable registers in programmable logic devices

2002-09-24

2004-03-09

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S038000, C326S040000

Reexamination Certificate

active

06703862

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to Programmable Logic Devices (PLDs). More particularly, the invention relates to efficient register implementations for PLDs.
BACKGROUND OF THE INVENTION
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLs, RAM, and so forth).
The CLBs, IOBS, interconnect, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect are configured. The configuration data can be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
One such FPGA, the Xilinx Virtex®-II FPGA, is described in detail in pages 33-75 of the “Virtex-II Platform FPGA Handbook”, published December, 2000, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.)
FIG. 1
is a simplified block diagram of a Virtex-II CLB
100
. The CLB includes four similar slices SLICE_
0
through SLICE_
3
. Each slice includes two 4-input function generators (
101
,
102
) which can be configured to function either as 4-input lookup tables or as distributed RAM blocks. When in RAM mode, the write process is controlled by write strobe generator
111
, which provides write strobe signals WS to the function generators (
101
,
102
). (In the present specification, the same reference characters are used to refer to terminals, signal lines, and their corresponding signals.) The RAM input data is supplied by direct input terminals RAM_DI_
1
and RAM_DI_
2
.
Each function generator (
101
,
102
) supplies an output signal to an associated multiplexer (MUX
1
, MUX
2
), which in turn supplies a data input to an associated memory element (
121
,
122
). Direct input terminals Reg_DI_
1
, Reg_DI_
2
also drive multiplexers MUX
1
, MUX
2
, respectively, allowing independent signals to be loaded into the memory elements. Multiplexers MUX
1
and MUX
2
are controlled by configuration memory cells (
131
,
132
). Thus, once the CLB is configured, only one of the function generator output signal and the direct input signal can provide data to the data input terminal of each memory cell.
Memory elements
121
,
122
are controlled by clock CK and clock enable CE signals (supplied by direct input terminals, not shown), and by memory control signals. The memory control signals of a Virtex-II memory element include a set/reset select signal SR_Sel (which determines whether the memory element is a set or a reset element), a set/reset enable signal SR_En (which initializes the memory element based on the value of the set/reset select signal), and a reverse enable signal SR_Rev (which initializes the memory element to the opposite state from that initiated by the signal SR_En). If both signals SR_En and SR_Rev are active, the signal performing the reset function takes precedence, and the signal performing the set function is ignored.
The value of the set/reset select signal SR_Sel is controlled by a configuration memory cell (
141
,
142
). Set/reset enable signal SR_En is supplied by a direct input terminal, as shown in FIG.
1
. Reverse enable signal SR_Rev is configurably supplied by the Reg_DI_
1
terminal, which, as noted above, can also be used to supply a direct input to the data input terminal of memory element
121
.
One feature of a CLB that can be important in some applications is the time required to load new data from the function generators into the memory elements. As seen in
FIG. 1
, the path between each function generator and the associated memory element traverses a multiplexer (MUX
1
, MUX
2
) that is needed to allow a data write from the direct input terminal (Reg_DI_
1
, Reg_DI_
2
). Thus, the direct write capability slows down all circuits that register the function generator output signal in the same slice, even when the direct write capability is not used.
Further, the MUX
1
, MUX
2
multiplexers are controlled by configuration memory cells
131
,
132
. Thus, as noted above, once the CLB is configured only one of the function generator output signal and the direct input signal can provide data to the data input terminal of each memory cell. To implement a user circuit that requires multiple signals optionally supplying data to the memory element, one or more multiplexers are typically added to the data path prior to the MUX
1
, MUX
2
multiplexers. The additional logic in the data path can require additional levels of logic, slowing down the overall operation of the user circuit.
It would be desirable to provide a CLB architecture for a PLD that would permit both direct register loading and the loading of data from a function generator of the CLB into an associated memory element without passing through a multiplexer such as MUX
1
and MUX
2
. It would further be desirable to provide a CLB architecture that would permit both direct register loading and the loading of data from a function generator of the CLB into an associated memory element under user control rather than as a configuration option. It would also be desirable to provide a register circuit implementation for existing CLB architectures that permits the same flexibility as the proposed new CLB architectures.
SUMMARY OF THE INVENTION
The invention provides efficient register implementations that are particularly useful in programmable logic devices (PLDs). The register circuits of the invention allow the loading of data values into a memory element using set and reset terminals in addition to the data input terminal of the memory element. Thus, traditional loading through the data input terminal is not slowed by the addition of the new functionality. PLD configurable logic blocks (CLBs) typically include function generators that drive the data input terminals of the associated memory elements. This traditional functionality can be retained while the new functionality allows an additional path through which data can be loaded to the memory element under user control.
According to a first aspect of the invention, a register circuit includes a memory element and a logical AND gate. Two register input terminals control the new load functionality, a load command input terminal that enables the load, and a load value input terminal that provides the new value to be loaded. The memory element has set and reset terminals in addition to the data and clock input terminals, and the reset function overrides the set function when both terminals provide active signals. The set terminal of the memory element is coupled to the load command input terminal of the register. The logical AND gate has input terminals coupled to the load command and load value input terminals, and an output terminal coupled to the reset terminal of the memory element.
Some register circuits are more than one bit wide. These embodiments include additional memory elements and additional logical AND circuits. The load command input signal is shared among all the memory elements, while a separate load value input signal is provided for each bit.
In some embodiments, the load value is inverted prior to the performance of the AND function. In these embodiments, the true value of the load value is loaded into the memory element. In other embodiments, the load value is not inverted prior to the logical AND gate. In these embodiments, the complement value of th

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