Efficient load/store buffer memory management in a computer...

Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering

Reexamination Certificate

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C710S056000, C711S153000

Reexamination Certificate

active

07853738

ABSTRACT:
A technique is disclosed for observing the data movement pattern in a peripheral device attached to a computer communications network data transmission switch, in order to arrive at a (statistical) determination of whether the peripheral device is being used as a “load intensive” device or as a “store intensive” device (or as neither type) over a defined time period. This determination is used to dynamically adjust (and re-allocate) the “outbound” and “inbound” buffer memory sizes assigned to a switch transmission port attached to the peripheral device, in cases where the device is operating in either “load intensive” or “store intensive” mode. The invention is applicable for use with all types of communications network switches (i.e. “Bridges”, “Hubs”, “Routers” etc.).

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patent: 2002/0120797 (2002-08-01), Fabre

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