Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Patent
1996-10-04
1999-08-03
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
711 5, G06F 1206
Patent
active
059338580
ABSTRACT:
An address line arrangement which uses weighted sets of mutually independent rather than binary address lines to enable the accessing of any number of targeted elements at one time. The elements in a device are divided into groups of elements. For a numerical example, assume four elements per group and eight groups per device. One set of four address lines is wired to access one or all groups in one half of the device and a second set of four lines will access one or all groups in the other half of the device. A third set of four address lines is wired to all elements and will access one, two or all elements in each group at a time. Each element is wired to one line in the first or second group and one line in the second or third group. Since all address lines can be individually turned on, one or more elements can be accessed at one time.
REFERENCES:
patent: 5355335 (1994-10-01), Katsuno
patent: 5440714 (1995-08-01), Wang
Tremblay et al., "A Three Dimensional Register File For Syperscalar Processors", 1995, pp. 191-201, IEEE.
Chan Eddie P.
Cunha Robert
Ellis Kevin L.
Xerox Corporation
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