Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-08-23
2003-08-19
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06609239
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to integrated circuit technology and in particular to arrangements of circuit elements within an integrated circuit.
BACKGROUND OF THE INVENTION
“Image response” is a well-known limitation in heterodyne wireless receivers. “Image response” occurs when an unwanted radio frequency (RF) component is mixed down to interface frequencies (IF) as a result of the process of mixing. The occurrence of “image response” imposes severe filtering requirements on a receiver. Image rejection mixer circuits have been devised to solve the problem of “image response.” Image rejection mixer circuits are widely used in many types of RF receivers. A typical image rejection mixer circuit is schematically illustrated in FIG.
1
.
An “image frequency” is a frequency that (when mixed with a local oscillator frequency) is converted to the same interface frequency (IF) as the desired RF channel frequencies. In an image rejection mixer circuit both the desired RF channel frequencies and the “image frequency” are frequency converted into two paths (an in-phase “I” path and a quadrature “Q” path). This is accomplished by mixers driven by quadrature phases (i.e., a sine wave (I) and a cosine wave (Q)) of the local oscillator frequency.
The mixer outputs are then filtered and phase shifted ninety degrees (90°) with respect to each other. The sum of these two signals will select the desired RF channel frequencies while suppressing the image frequency.
The extent of suppression of the image frequency that can be achieved is a critical quality of a receiver. The extent of suppression of the image frequency that can be achieved depends heavily on the gain and phase matching between the two mixer paths. In direct down receivers (i.e., zero IF receivers) any imbalance between the signals in the I path and in the Q path can be very critical due to large direct current (DC) errors introduced into the down converted output.
An image rejection mixer circuit is usually implemented in an integrated circuit.
FIG. 2
illustrates a conventional arrangement for laying out two gain blocks and two mixer blocks of an image rejection mixer circuit. It is well known that matching between identical blocks in an integrated circuit depends heavily on the relative position of the blocks with respect to each other. Traditionally, integrated circuit mask designers lay out each signal path independently. The completed blocks of each signal path are then placed next to each other. This is an efficient approach to the actual process of laying out the blocks. However, this approach results in non-optimum matching characteristics between the blocks.
It would be desirable to provide an improved integrated circuit layout in an image rejection mixer circuit. It would also be desirable to provide an improved integrated circuit layout in other types of circuits that have an I path and a Q path. It would be desirable to provide an improved integrated circuit that is capable of providing improved matching between an I path and a Q path in radio receiver circuits.
SUMMARY OF THE INVENTION
The apparatus and method of the present invention is capable of providing improved matching between an I path and a Q path in a radio receiver circuit. The apparatus generally comprises at least one circuit element that is divided into a first half strength circuit element located in a first area of a module and a second half strength circuit element located in a second area of the module. The first and second areas are oppositely located with respect to a central area of the module and minimize component mismatch by averaging out process gradients within the module.
It is an object of the present invention to provide an improved integrated circuit layout in an image rejection mixer circuit.
It is also an object of the present invention to provide an improved integrated circuit layout in a circuit of the type having an I path and a Q path.
It is another object of the present invention to provide an apparatus and method for providing improved matching between an I path and a Q path in a radio receiver circuit.
Other objects and advantages of the invention will become apparent as the description proceeds.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms “include” and “comprise” and derivatives thereof, mean inclusion without limitation, the term “or” is inclusive, meaning “and/or”; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term “controller,” “processor,” or “apparatus” means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.
REFERENCES:
patent: 5148180 (1992-09-01), Beyer et al.
patent: 6226509 (2001-05-01), Mole et al.
Levin Naum
National Semiconductor Corporation
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