Efficient implementation of timers in a multithreaded processor

Details Efficient implementation of timers in a multithreaded processor Efficient implementation of timers in a multithreaded processor

2007-02-13

2007-02-13

Elmore, Reba I. (Department: 2189)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S219000

Reexamination Certificate

active

10881225

ABSTRACT:
A method and mechanism for managing timers in a multithreaded processing system. A storage device stores a plurality of count values corresponding to a plurality of timers. A read address generator is coupled to convey a read address to the storage device. The read address generator is configured to maintain and increment a first counter. In response to determining the counter does not equal a predetermined value, the mechanism conveys a first read address for use in accessing a count value in the storage device. In response to determining the count equals the predetermined value, the mechanism conveys a second read address for use in accessing a count value in the storage device. The predetermined value is utilized to repeat accesses to a given count value a predetermined number of times.

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