Efficient implementation of a decision directed phase locked...

Details Efficient implementation of a decision directed phase locked... Efficient implementation of a decision directed phase locked...

2005-10-18

2005-10-18

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000

Reexamination Certificate

active

06956924

ABSTRACT:
A decision directed phase locked loop (DD-PLL) is efficiently implemented in a communication receiver. The phase locked loop includes an enhanced block decoder inside a phase detector which takes in the baseband complex samples and the current channel phase estimate (or the tracked phase) and generates a feedback phase error term. A loop filter filters the phase error terms and a phase accumulator updates the tracked phase estimate on each iteration of the loop.

REFERENCES:
patent: 6236687 (2001-05-01), Caso et al.
patent: 6307905 (2001-10-01), Agazzi
patent: 6335952 (2002-01-01), Lee et al.
patent: 6603349 (2003-08-01), Carrozza et al.
patent: 6628276 (2003-09-01), Elliott
patent: 6781447 (2004-08-01), Linsky et al.
patent: 2003/0103582 (2003-06-01), Linsky et al.

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