Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Patent
1998-05-29
1999-09-14
Pan, Daniel H.
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
712227, 712 11, 714 47, 714 54, G06F 934, G06F 9345, G06F 1202
Patent
active
059516771
ABSTRACT:
A programmable logic device, such as a digital signal processor (DSP) (130), having a Euclidean array unit (115; 115') is disclosed. The Euclidean array unit (115; 115') is arranged to perform finite field arithmetic functions useful in determining the greatest common factor among two polynomial series, in a sequential fashion beginning with a highest order pair of operands (A.sub.0, B.sub.0) and proceeding along the sequence. A source register (SRC) receives each pair of operands, and the results are stored in a result register (RES) in reverse order, prior to writing the results in memory. As a result, B result values are stored in the same location as the A input operand, and vice versa. This reversal of memory locations permits successive passes of the Euclidean operation to be carried out with simple incrementing of the starting byte address (SBA) at which the operands are located in memory, thus eliminating the need for large memory shifts. The Euclidean array unit (115') may also operate upon more than one A and B input operand at a time, for further efficiency.
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Araki, et al., "Modified Euclidean Algorithm having High Modularity and Minimum Register Organization", Trans. IEICE, vol. E-74, No. 4 (IEICE, 1994), pp. 731-737.
Shiell Jonathan H.
Wolf Tod D.
Donaldson Richard L.
Laws Gerald E.
Marshall, Jr. Robert D.
Pan Daniel H.
Texas Instruments Incorporated
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