Efficient generation of optimum test data

Details Efficient generation of optimum test data Efficient generation of optimum test data

2000-11-30

2003-03-18

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06536020

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to testing of LSI circuits, and particularly relates to a method of generating optimum test data.
2. Description of the Related Art
As circuit density of LSI circuits increases, system LSI circuits are used in increasing numbers where the system LSI circuits include a microprocessor unit (MPU), an internal circuit, and a RAM, and has a micro-program stored in the RAM, which allows the microprocessor to operate in accordance with instruction codes of the micro-program, thereby controlling the internal circuit.
A system LSI circuit is a highly integrated circuit implemented as a single chip, on which the MPU, the memory, and various circuits are mounted. The greater the circuit density, the greater the size of test data necessary for conducting tests. It is necessary, therefore, to conduct an efficient test by preparing an efficient set of data no more than necessary for conducting the test.
FIG. 9
is a flowchart showing a related-art process of LSI development.
At a step ST_a, a circuit design of an LSI circuit is determined by a design engineer using a workstation. In order to check proper operation of the designed circuit in terms of operation logic, a logic simulation is carried out on the workstation (at a step ST_b). At a step ST_c, after appropriate corrections are made in response to the logic simulation, a layout of the circuit is designed by using the workstation in order to arrange various circuit elements within the circuit space. At a step ST_d, simulation of gate operations is carried out by taking into account line capacitance of the signal lines of the circuit layout. At a step ST_e, test data is generated on the workstation. Here, the test data is to be fed into a LSI tester device at a subsequent stage when the LSI tester device is used to test an actually manufactured LSI circuit. The test data indicates timings of signals, including data of input signals that are supplied to input terminals of the tested LSI circuit, and including data of output signals that are expected to be output from the output terminals of the tested LSI circuit.
When the design of the LSI circuit is completed after the process described above, data of the circuit design is released to the process of LSI-chip manufacture (e.g., released to an LSI-chip manufacturer) at a step ST_f. Here, the released data of the circuit design include circuit data, physical LSI data (e.g., regarding pins and test terminals), and the test data of an LSI tester device.
At a step STE_g, the circuit data and the LSI physical data are used in the process of manufacturing LSI chips to actually manufacture an LSI chip. At a step ST_h, the test data is fed into an LSI tester device that is commercially available. At a step ST_i, the manufactured LSI chip is set in the LSI tester device, and tests are conducted by use of the test data.
FIG. 10
is a block diagram showing an example of an LSI circuit.
FIG. 11
is a flowchart of a process of generating test data for testing the LSI circuit shown in
FIG. 10. A
method of generating the test data for testing the LSI circuit of
FIG. 10
will be described below.
In the example of the LSI circuit shown in
FIG. 10
, a micro-program to be executed by a microprocessor is loaded to a RAM (e.g., SRAM) of the LSI circuit when the micro-program is supplied from a ROM provided outside the LSI circuit at the time of power-on.
In
FIG. 10
, an LSI
80
is connected to a ROM
81
that stores a micro-program therein, and has a terminal that is used for micro loading. A power-on-reset circuit
83
supplies a power-on-reset signal. The LSI
80
is also connected to a 2
nd
cache
84
and an I/O (input/output) device
85
. The LSI
80
includes a micro loading circuit
80
a
, a set of various internal circuits
80
b
, a processing circuit
80
c
having an MPU (microprocessor unit) and an SRAM for loading a micro-program, and a set of various circuits
80
d
including a 1
st
cache, a 1
st
-cache control, a 2
nd
-cache control, and an I/O control.
The process shown in
FIG. 11
is carried out to generate test data by simulating the circuit of
FIG. 10
on the workstation, and the generated test data is used for testing an actually manufactured LSI circuit.
After starting the simulation, at a step S
1
, a micro-program to be transferred to the LSI circuit
80
is prepared in the ROM
81
. At a step S
2
, a power-on-reset signal is supplied to the LSI circuit
80
. In response, at a step S
3
, the data (i.e., the micro-program) is transferred from the ROM
81
to the SRAM of the processing circuit
80
c
of the LSI
80
. This transfer is carried out by the micro loading circuit
80
a
, and the micro-program is loaded to all the area of the SRAM. This micro-program is a set of instructions that are used by the MPU to operate. At a step S
4
, the MPU starts operation thereof by following the instructions of the micro-program stored in the SRAM. At a step S
5
, a check is made by using a minimum necessary set of instructions of the micro-program as to whether various circuits operate properly. At a step S
6
, a check is made as to whether debugging of the micro-program is completed. If there is a bug, correction is made, and, then, the procedure goes back to the step S
1
followed by the series of steps S
2
through S
5
of the simulation. Namely, the data (i.e., the micro-program) is transferred again from the ROM
81
to the SRAM of the processing circuit
80
c
of the LSI
80
, and a check is made with regard to the proper operation of the circuits.
The method of generating test data for a system LSI circuit as described above has drawbacks as follows.
FIGS. 12A and 12B
are illustrative drawings for explaining the drawbacks of the related art.
In the related art method of generating test data, data transfer from the ROM to the RAM needs to be carried out each time the micro-program is debugged. Namely, as shown in
FIG. 12A
, the total time length of the simulation on the workstation is represented as (time length of data transfer from ROM to RAM+time length required for checking operation of circuits by use of instructions stored in RAM)×(the number of debugging operations).
In this case, the time length of data transfer from the external ROM to the internal RAM (SRAM) accounts for most of the simulation time. Since a series of steps of the simulation need to be repeated as many times as there are debugging operations, the total time of the simulation tends to be lengthy.
Further, the time length of data transfer itself is quite lengthy in the related-art method. Not all of the instructions of the micro-program are necessary for the purpose of conducting tests using the tester device. However, since the related-art method sequentially transfers all the micro-program contents from the ROM to the RAM, the size of data to be transferred is quite large.
FIG. 12B
shows the way the data of the external ROM is transferred to and stored in the RAM area for storing a micro-program. In this example, data of four addresses in the ROM are stored at one address in the RAM. Data at each address in the ROM is comprised of 8 bits, and data at each address in the RAM is comprised of 32 bits. Not all of the data stored in the RAM are used as the test data. In this example, data (i.e., the micro-program) stored at the addresses 00001 and 00003 are not used for the test purposes.
Accordingly, there is a need for a method of generating test data for testing an LSI circuit that can generate test data efficiently, thereby shortening the simulation time and improving debugging efficiency.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a method of generating test data that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be set forth in the description which follows, and in part will become apparent from the description and the accompanying drawi

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