Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-12-06
2009-12-08
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S202000
Reexamination Certificate
active
07631147
ABSTRACT:
Various operations are disclosed for improving the operational efficiency of address mapping caches, such as translation lookaside buffers, in a multiprocessor environment. When an address mapping translation is invalidated, unnecessary address mapping cache flushes are avoided by signaling only those processors operating in a virtual machine monitor mode to flush their address mapping caches. Address mapping cache flushes for processors operating in guest modes are postponed until the processor enters a virtual machine monitor mode. Optionally, a counter is maintained for each processor and incremented each time the processor enters virtual machine monitor mode. When an address mapping cache is invalidated, a snapshot of the counter values is stored. When an new address translation for an invalidated address translation is requested, the snapshot is compared with the current value of a counter to determine whether the address mapping cache associated with the counter has been flushed since the invalidation.
REFERENCES:
patent: 4733348 (1988-03-01), Hiraoka et al.
patent: 5317705 (1994-05-01), Gannon et al.
patent: 5317754 (1994-05-01), Blandy et al.
patent: 5428757 (1995-06-01), Sutton
patent: 5455922 (1995-10-01), Eberhard et al.
patent: 5805790 (1998-09-01), Nota et al.
patent: 5906001 (1999-05-01), Wu et al.
patent: 5928353 (1999-07-01), Yamada
patent: 6510508 (2003-01-01), Zuraski, Jr. et al.
patent: 6907600 (2005-06-01), Neiger et al.
patent: 7069389 (2006-06-01), Cohen
patent: 7484073 (2009-01-01), Cohen et al.
patent: 7509475 (2009-03-01), Shinohara et al.
patent: 2004/0025161 (2004-02-01), Chauvel et al.
patent: 2006/0259732 (2006-11-01), Traut et al.
Black, D.L. et al., “Translation Lookaside Buffer Consistency: A Software Approach,”ACM, 1989, 113-122.
Chang, M-S et al., “Lazy TLB Consistency for Large-Scale Multiprocessors,”IEEE, 1997, 308-315.
Rosenburg, B., “Low-Synchronization Translation Lookaside Buffer Consistency in Large-Scale Shared-Memory Multiprocessors,”ACM, 1989, 137-146.
Bataille Pierre-Michel
Microsoft Corporation
Woodcock & Washburn LLP
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