Efficient extractor for post-layout simulation on memories

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06874132

ABSTRACT:
Embodiments of the present invention relate to a computer-controlled method for extracting cell parasitic characteristics for netlist back-annotation in a circuit that comprises a row and column array of repeated cells. The method comprises the steps of generating parasitic and connection data for a row and a column of said cells in the arrayed circuit, duplicating the generated parasitic data for an additional row and an additional column in the arrayed circuit; synthesizing connection data for the additional row from a connected cell in that additional row; synthesizing connection data for the additional column from a connected cell in that additional column, and making the generated parasitic data and the synthesized connection data available for subsequent back-annotation of the netlist.

REFERENCES:
patent: 6184711 (2001-02-01), Graef et al.
patent: 6289412 (2001-09-01), Yuan et al.
patent: 6463571 (2002-10-01), Morgan
patent: 6499129 (2002-12-01), Srinivasan et al.
patent: 6505323 (2003-01-01), Lipton et al.
patent: 6543032 (2003-04-01), Zolotykh et al.

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