Electrical computers and digital processing systems: memory – Address formation – Slip control – misaligning – boundary alignment
Reexamination Certificate
2011-08-09
2011-08-09
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Address formation
Slip control, misaligning, boundary alignment
C711S005000, C711S127000, C711S157000, C711SE12079, C711SE12047, C711S220000
Reexamination Certificate
active
07996646
ABSTRACT:
In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation. The first even mask identifies bytes within the first even byte range that are written by the store memory operation, and wherein the first odd mask identifies bytes within the first odd byte range that are written by the store memory operation.
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Chang Po-Yung
Mehta Anup S.
Murray Daniel C.
Yeh Tse-Yu
Apple Inc.
Bragdon Reginald G
Merkel Lawrence J.
Meyertons Hood Kivlin Kowert & Goetzel P.C.
Talukdar Arvind
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