Efficient dual port DRAM cell using SOI technology

Details Efficient dual port DRAM cell using SOI technology Efficient dual port DRAM cell using SOI technology

2000-08-03

2001-11-13

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S052000, C365S063000, C365S230050

Reexamination Certificate

active

06317358

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to dynamic random access memory (“DRAM”) cells, particularly to a dual port DRAM cell having reduced architecture utilizing silicon on insulator (“SOI”) structure.
DISCUSSION OF THE RELATED ART
As the data processing speed of computer systems increase, the need for faster memory speeds also increases. Conventional (or single port) DRAMs, due to their high density and relatively low manufacturing cost, are presently used for the majority of memory applications. Conventional DRAMs, however, are not feasible for many growing memory applications. While cost effective, conventional DRAMs have a lower operating speed relative to other memory types.
In a typical single port configuration, as shown in
FIG. 1
, a DRAM cell
100
consists of an access transistor
101
, a storage capacitor
120
, a digit line
111
and a wordline
106
. During a write access, a wordline enable signal is asserted on wordline
106
thereby turning on transistor
101
. A data signal is provided on digit line
111
. This signal is routed through transistor
101
and stored in capacitor
120
. During a read access, a wordline enable signal is asserted on wordline
106
to turn on transistor
101
. The data signal stored in capacitor
120
is routed to digit line
111
through transistor
101
. This data signal is amplified by a sense amplifier (not shown) and then provided to the device initiating the read access.
As noted, the single port cell DRAM illustrated in
FIG. 1
while having many advantages is relatively slow. As a result, faster memory devices have been developed which include dual-port DRAMs (called video RAMs, or VRAMs, in some instances). Dual-port DRAMs provide speed advantages over conventional DRAMs by providing an additional input/output port to the memory array. In conventional DRAMs, read and write operations may never occur simultaneously, as both operations occur through a single random access port, as discussed above. In contrast, in a dual-port DRAM, the second port (most often a serial port) is provided in addition to the random access port. Data is read and written by transferring an entire array row at one time between a serial shift register and the array.
FIG. 2
is a schematic diagram of a conventional dual-port DRAM cell
200
. Cell
200
consists of write access transistor
201
, read access transistor
202
and storage capacitor
220
. The operation of cell
200
is similar to that of single port DRAM cell
100
, except the read and write accesses are performed at two separate dedicated ports. The write port is defined by the write digit line
211
and write wordline
206
. The read port is defined by the read digit line
212
and read wordline
205
.
During a write access, a write wordline enable signal is asserted on write wordline
206
, thereby turning on write transistor
201
. A data signal is provided to capacitor
220
through write digit line
211
and write transistor
201
. During a read access, a read wordline enable signal is asserted on read wordline
205
. If a logic high data value is stored in capacitor
220
, read transistor
202
turns on and the logic high wordline enable signal on read wordline
205
is transmitted to read digit line
212
. If a logic low data value is stored in the capacitor
220
, transistor
202
is not turned on, and read digit line
212
is left floating (i.e. at a logic low value).
However, even though dual port DRAMs have higher operating speeds, their cells are more complex in design and are larger in size relative to a conventional single port DRAM cell. Typically, a dual port DRAM cell occupies 16 square features (F
2
). Hence, what is needed is a dual port DRAM with a reduced structure size.
SUMMARY OF THE INVENTION
The present invention proposes a dual port DRAM SOI structure with reduced architecture of no more than 8 F
2
by utilizing two separate metallization layers above and below an upper surface of the silicon on insulator layer.
In a memory cell of the invention, each storage capacitor is connected by an associated access transistor, to one of two bit lines. Thus, a first access transistor connects the capacitor through an upper bit line contact to a first digit line which runs above the upper surface of the silicon on insulator layer while a second access transistor connects the capacitor through a lower bit line contact to a second digit line which runs below the upper surface of the silicon on insulator layer.
The above advantages and features of the invention will be more clearly understood from the following detailed description which is provided in connection with the accompanying drawings.


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H. Hoenigschmid et al., “A 7F2Cell and Bitline Architecture Featuring Titled Array Devices and Penalty-Free Vertical BL Twists for 4Gb DRAM's”, 1999 Symposium on VLSI Circuits Digest of Technical Papers, pp. 125-126.
800 Mb/s/pin SLDRAM, 1999, pp. 1-32.

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