Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-10
2007-04-10
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10795384
ABSTRACT:
There is provided a method of solving a SAT problem comprising partitioning SAT-formula clauses in the SAT problem into a plurality of partitions. Each of said plurality of partitions is solved as a separate process each, thereby constituting a plurality of processes where each of said process communicates only with a subset of the plurality of processes.
REFERENCES:
patent: 5469367 (1995-11-01), Puri et al.
patent: 6415430 (2002-07-01), Ashar et al.
patent: 6442732 (2002-08-01), Abramovici et al.
patent: 6496961 (2002-12-01), Gupta et al.
Ashar Pranav
Ganai Malay
Gupta Aarti
Yang Zijiang
Do Thuan
NEC Laboratories America, Inc.
Tat Binh
LandOfFree
Efficient distributed SAT and SAT-based distributed bounded... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Efficient distributed SAT and SAT-based distributed bounded..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient distributed SAT and SAT-based distributed bounded... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3745768