Efficient direct replacement cell fault tolerant architecture

Details Efficient direct replacement cell fault tolerant architecture Efficient direct replacement cell fault tolerant architecture

1999-08-18

2000-11-28

Wright, Norman M.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 48, 714 25, H02H 305

Patent

active

061548553

ABSTRACT:
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to by organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into single monolithic entity.

REFERENCES:
patent: 5497465 (1996-03-01), Chia et al.
patent: 5748872 (1998-05-01), Norman
patent: 6021511 (2000-02-01), Nakano
patent: 6038682 (2000-03-01), Norman

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