Efficient detection of multiple assertions in a bus

Details Efficient detection of multiple assertions in a bus Efficient detection of multiple assertions in a bus

2007-07-03

2007-07-03

Le, Vu A. (Department: 2824)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus interface architecture

C710S107000

Reexamination Certificate

active

10796957

ABSTRACT:
A mechanism detects multiple assertions in a bus efficiently by encoding each of N bus lines with log2(N) pairs of bit lines.

REFERENCES:
patent: 6018810 (2000-01-01), Olarig
patent: 6489900 (2002-12-01), Shin et al.
patent: 6557068 (2003-04-01), Riley et al.
patent: 6721918 (2004-04-01), Self et al.
patent: 7003605 (2006-02-01), Craft et al.

Affiliated with

Also associated with

Rating

Efficient detection of multiple assertions in a bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Efficient detection of multiple assertions in a bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient detection of multiple assertions in a bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3751793