Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-12
2002-05-28
Teska, Kevin J. (Department: 2123)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06397373
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a manufacturing process and more particularly to Design Rule Checking in a manufacturing process.
2. Description of Related Art
U.S. Pat. No. 5,440,720 of Baisuck et al., assigned to Cadence Design Systems, for “Architecture and Method for Data Reduction in a System for Analyzing Geometric Databases” shows a method for data reduction.
U.S. Pat. No. 5,483,603 of Luke et al. for “System and Method for Automatic Optical Inspection” shows a method for automatic optical inspection.
U.S. Pat. No. 5,590,049 assigned to Cadence Design Systems of Arora for “Method and System for User Programmable Design Verification for Printed Circuit Boards and Multichip Modules” shows a method for design verification.
U.S. Pat. No. 5,613,102 of Chiang et al. “Method for Compressing Data for Use in Performing VLSI Mask Layout Verification” teaches a method for compressing data for layout verification.
U.S. Pat. No. 5,754,826 of Gamal et al for “CAD and Simulation System for Targeting IC Designs to Multiple Fabrication Processes” describes Design Review Check (DRC) using Dracula (TM) from Cadence starting with a GDSII file (a polygon level description). Errors are reported.
U.S. Pat. No. 5,764,793 of Omae et al. for “Method of and Apparatus for Inspecting Pattern Defects” describes a design rule check circuit for “DRC” inspection which uses a compare check method relative to a reference pattern image.
U.S. Pat. No. 5,781,446 of Wu for “System and Method for Multi-Constraint Domain Electronic System Design Mapping” describes at Col. 2, lines 29-39, a physical spacing DRC performed to verify that adequate spacing exists between adjacent components to accommodate conductor routing channels or the handling head of a pick-and-place PCB manufacturing system.
U.S. Pat. No. 5,787,006 of Chevallier et al. for “Apparatus and Method for Management of Integrated Circuit Layout Verification Processes” describes DRC and Layout Versus Schematic (LVS) verification procedures, in considerable detail.
SUMMARY OF THE INVENTION
A method of reviewing a Design Rule Check (DRC) for every new coming product is very important in contemporary fabrication plants.
However with in currently available review methods for use with the Design Rule Check (DRC), one needs to view error flags one-by-one. This is almost impossible to view all for any chips which is designed by current chip design methodology.
This invention provides a new way to overcome this problem by revising the current method.
In view of the very large scale of contemporary integrated circuit devices, it is so time consuming that it is almost impossible to view all error flags one-by-one, with the current state of the art of chip design methodology where thousands of error flags may be present. This invention provides a method for overcoming the problem of viewing error flags with a reasonable expenditure of resources.
It is an object of this invention to provide DRC review with full coverage of flagged errors.
It is another object of this invention to improve the efficiency of the process of DRC review.
The present invention teaches use of the Cadence DRACULA program to run DRC using a GDSII file providing geometrical classification of patterns on a mask or reticle. A program for classification of error flags and generation of an output file grading the error flags is provided; and means and process functions are provided for viewing selected error flags.
In accordance with this invention, a method is provided for performing a design review checking operation and analyzing the resultant data comprising as follows:
Perform a Design Review Check (DRC) operation describing chip features and generating flags for violation sites including patterns and paths.
Execute pattern analysis and grade classification steps for the violation sites.
Generate a vector array for each chip feature for each of the violation sites.
Compare the vector arrays to determine whether the degree of similarity of geometries of chip features of violation sites meets one of a set of criteria.
Classify the violation sites into classes with similar criteria.
Select representative arrays from each class of violation sites to provide an output.
Calculate distance from a violation site from the origin in a two-dimensional array.
Give a grade to each vector array to indicate the level of seriousness of the rule violation by the site.
Use a layout viewer to view the error flags generated by pattern analysis and grade classification steps.
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Suzuki et al.; “A practical online design rule checking system”; IEEE Proc Design Automation Conf.; pp. 246-252, Jun. 1990.*
Lu et al.; “A new algorithm for sorting problem with reformed CAM”; IEEE ISCAS '95; pp. 1045-1048, Apr. 1995.*
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Liu Chin-Kai
Tseng Fouriers
Ackerman Stephen B.
Jones Hugh
Jones II Graham S.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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