Efficient data transfer mechanism for input/output devices

Details Efficient data transfer mechanism for input/output devices Efficient data transfer mechanism for input/output devices

1997-05-01

2000-04-11

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

710 34, 710 35, G06F 1314

Patent

active

060498420

ABSTRACT:
A method for transferring data between non-contiguous buffers in a memory and an I/O device via a system I/O bus uses a descriptor queue stored in memory. Each descriptor points to a buffer and includes the length of the buffer. The I/O device is provided with the base address of the queue, the length of the queue and a current address which at initialization is the same as the base address. When data is to be transferred a device driver located in the processor sends the number of available descriptors (DescrEnq) to the I/O device which accesses the descriptors individually or in burst mode to gain access to the data buffers identified by the descriptors.

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IBM Technical Disclosure Bulletin V36 #1 Jan. 1993 "Asynchronous/Queued I/O Processor Architecture".

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