Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-07-05
2004-08-10
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S052000, C710S005000, C710S006000, C710S020000, C710S021000, C710S029000, C710S054000
Reexamination Certificate
active
06775722
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
This invention is related to network switch fabrics, and more specifically, to data control and retrieval from the buffering mechanisms contained therein.
2. Background of the Art
The evolution of the Internet and other global communication networks continue to attract an ever-increasing number of nodal entities which place strategic importance on the viability of such networks for the communication of information for commercial and personal use. Such information places higher demands on the network infrastructure to ensure not only that the information arrives at the desired destination, but that it arrives in a timely manner.
Most modern switching devices can move information at wire speed and it is a goal is to ensure that the switching device is not the bottleneck of network data flow. However, with network bandwidth requirements pushing the development and implementation of faster transmission technologies e.g., Gigabit Ethernet, internal data flow of such switching devices becomes more important in order to maintain data throughput at such wire speeds.
Many switching devices utilize queues for the temporary storage of data while processing logic has time to sort out the destination information, and to send the data on its way. Consequently, queuing performance is very important.
What is needed is an architecture that provides efficient queuing performance that ensures overflow will not occur in Gigabit Ethernet implementations.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein, in one aspect thereof, comprises an architecture for data retrieval from a plurality of coupling queues. At least first and second data queues are provided for receiving data thereinto. The data is read from the at least first and second data queues with reading logic, the reading logic reading the data according to a predetermined queue selection algorithm. The data read from by reading logic and forwarded to an output queue.
REFERENCES:
patent: 5920572 (1999-07-01), Washington et al.
patent: 6483846 (2002-11-01), Huang et al.
patent: 2002/0035656 (2002-03-01), Tate
Kuo Jerry
Wu David
Gaffin Jeffrey
Knapp Justin
Tucker Ellis & West LLP
Zarlink Semiconductor V. N. Inc.
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