Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-09-16
2001-06-12
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
Reexamination Certificate
active
06247089
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to network interfaces, and more specifically to arrangements in network interfaces for transferring data using Direct Memory Access (DMA) techniques via a host bus between a host memory and the network interface.
2. Description of Related Art
Network interfaces connecting a host computer to a network such as an Ethernet-type or IEEE 802.3 network, typically utilize a host bus to transfer information between a host memory and the network interface. Two types of bus transfers may be used, namely master mode and slave mode. In master mode, a transaction or transfer of information over the bus is initiated by a master, which arbitrates for use of the bus along with other masters requesting use of the bus.
One example of a host bus is the peripheral component interconnect (PCI) local bus. A single transaction or transfer of information over a PCI bus comprises an address phase followed by one or more contiguous data phases. In conducting transactions, the PCI bus makes use of a centralized, synchronous arbitration scheme in which each PCI master arbitrates for each transaction using a unique request and grant signal. These signal lines are attached to a central arbiter and a request-grant handshake is used to grant the master access to the bus. A common sequence for a request-grant handshake is begun when the master asserts a request signal to request use of the bus. A host CPU will respond with a grant signal, followed by assertion of a frame signal that in combination identify to the network interface when the bus is available for data transfers.
The period of time between the assertion of the request signal and the grant signal is known as arbitration latency. The arbitration latency may delay transfer of data by the network interface on the host bus, and is based on the arbitration algorithm used by the host CPU, the relative priority compared to other devices accessing the bus, and system utilization. Since the PCI bus specification does not dictate a particular arbitration algorithm, arbitration latency is variable. Prior art approaches to arbitration simply wait until the frame signal is asserted before transferring data to a target via the host bus. Since the arbitration latency is a function of the arbitration algorithm, this approach causes unnecessary arbitration delays which causes additional wait states to be experienced during the transfer.
SUMMARY OF THE INVENTION
There is a need for an arrangement that minimizes arbitration delays and wait states during data transfers by a network interface on a host bus.
There is also a need for an arrangement that provides the data to be transferred, between a network interface and a host memory via the host bus, by loading the data into holding registers in the network interface prior to the readiness of the host memory to receive data based on the network interface detecting signals normally asserted on the network in arbitrating for use of the network. There is also a need for an arrangement that provides for data loaded in holding registers to be output onto the host bus, and new data to be loaded in the holding registers for later output, based on a host memory ready signal provided by the host memory indicating a readiness of the host memory to receive data transferred via the host bus, to minimize wait states during host memory state transitions.
These and other needs are attained by the present invention, where fiame data is stored in network interface holding registers in response to a memory advance signal generated by a bus access controller, and where the frame data is selectively output onto the host bus based on the ability of the host memory to receive the data. The selective output of data is based on a successful transfer of data on the host bus during a preceding clock cycle.
According to one aspect of the present invention, a method in a network interface having a bus access controller, for transferring data between a target via a host bus, comprises generating a memory advance signal based on at least one of a transfer request signal generated in the network interface by a bus access controller, a grant signal on the host bus following the transfer request signal, and a ready signal on the host bus indicating a ready condition by the target to receive data. The method further includes first storing a first data set, supplied from a buffer memory, in a first holding register in response to the assertion of the memory advance signal during a first host bus clock cycle, second storing the first data set stored in the first holding register into a second holding register in response to assertion of the memory advance signal during a second host bus clock cycle following the first host bus clock cycle, third storing a second data set in the first holding register in response to assertion of the memory advance signal during the second host bus clock cycle, and selectively supplying one of the first and second data sets to an output holding register for output on the host bus based on detection the memory advance signal. Use of the advance signal to store data sets in the first holding register enables frame data to be loaded into the holding register, for output onto the host bus, before receiving a target ready signal. Moreover, the selective supply from the first or second holding register enables data from the network interface to be transferred the next clock cycle after receiving the target ready signal, without the necessity of a wait clock cycle to load the data from buffer memory for output onto the host bus.
Another aspect of the present invention provides a network interface for transferring received data via a host bus to a target, comprising a memory configured for storing a plurality of data sets, a bus access controller for generating an advance signal based on at least one of a transfer request signal generated by the network interface, a grant signal on the host bus following the transfer request signal, and a ready signal on the host bus indicating a ready condition by the target to receive data, a first holding register for storing a first data set transferred from the memory in response to assertion of the advance signal during a first clock cycle, a second holding register for storing the first data set from the first register in response to assertion of the advance signal during a second clock cycle following the first clock cycle, the first register storing a second data set output from the memory in response to assertion of the advance signal during the second clock cycle, and an output holding register for selectively storing one of the first and second data sets for output on the host bus based on detection of the memory advance signal. The bus access controller selectively outputs the data set from the first or second holding register to the output holding register for output to the host bus to accommodate variances in the frequency of target ready signals received from the target and detected by the bus access controller. Hence, the output holding register is able to output data onto the host bus with zero wait states following the grant signal, despite any arbitration latency that may be encountered on the host bus.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
patent: 5727149 (1998-03-01), Hirata et al.
patent: 5857075 (1999-01-01), Chung
patent: 6061768 (2000-05-01), Kuo et al.
patent: 6145016 (2000-11-01), Lai et al.
Chiang John
Kuo Jerry Chun-Jen
Advanced Micro Devices , Inc.
Auve Glenn A.
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