Efficient communication of transaction types using separate...

Details Efficient communication of transaction types using separate... Efficient communication of transaction types using separate...

1998-11-03

2001-01-16

Lee, Thomas C. (Department: 2782)

Electrical computers and digital data processing systems: input/

Input/output data processing

Frame forming

C710S004000, C710S005000

Reexamination Certificate

active

06175884

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of computer systems. More particularly, this invention pertains to the field of communicating between devices in a computer system.
BACKGROUND OF THE INVENTION
Prior computer systems typically rely on standardized busses, such as the Peripheral Component Interconnect (PCI) bus, to allow computer system chipset components to communicate one with another. For example, a transaction originating at a processor and intended for a disk drive might first be delivered to a first chipset component that serves as an intermediary between the processor bus and a PCI bus. The first chipset component would then deliver the transaction over the PCI bus to a second system chipset component which would then deliver the transaction to the disk drive.
Busses such as the PCI bus also provide for communication with other computer system devices such as graphics controllers and network adapters. Because busses such as the PCI bus must interface with a variety of component types, each with varying requirements, they are not necessarily optimized for allowing communication between chipset components. Further, chipset manufacturers who rely on standardized busses such as the PCI bus must adhere to bus standards in order to ensure compatibility with other components, and are not at liberty to make substantial changes in how the chipset components communicate with each other. Another issue that faces chipset component manufacturers in designing and manufacturing chipset components is the need to conform to standardized supply and signaling voltages when relying on busses such as PCI for communication between chipset components, thereby locking the manufacturers into certain design practices and manufacturing technologies.
Prior computer systems that rely on standardized busses such as PCI for communication between chipset components also typically have no mechanism for communicating that a particular transaction is isochronous and should be handled in a manner that will ensure an adequate level of quality of service. Deterministic quality of service is particularly important for emerging applications that rely on isochronous services in the system to move fixed amount of data on a regular basis. In prior systems, the notion of isochronous transactions is contained within subsystems such as USB host controllers and IEEE 1394 host controllers, and there is no mechanism to extend this notion up to the point where transactions are serviced (the main memory subsystem).
SUMMARY OF THE INVENTION
A method and apparatus for communicating transaction types between hubs in a computer system is disclosed. The apparatus includes a data path input/output unit to output a packet header. The packet header includes a request/completion field to indicate whether the packet header is a request packet header or a completion packet header. The packet header also includes a read/write field to indicate whether the packet header is for a read packet or for a write packet. The read/write field further indicates whether a length of data is to follow the packet header. The packet header further includes a data length field to indicate the length of data.


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