Efficient clocking scheme for ultra high-speed systems

Details Efficient clocking scheme for ultra high-speed systems Efficient clocking scheme for ultra high-speed systems

2005-07-18

2008-11-18

Perveen, Rehana (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S600000

Reexamination Certificate

active

07454646

ABSTRACT:
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.

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S. Pellerano; S. Levantino; A 13.5-mW 5-GHz Frequency Synthesizer With Dynamic-Logic Fequency Divider; Feb. 2004; 6 pages.

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