Electrical computers and digital data processing systems: input/ – Access locking
Reexamination Certificate
2000-10-18
2004-02-10
Vo, Tim (Department: 2181)
Electrical computers and digital data processing systems: input/
Access locking
C710S240000
Reexamination Certificate
active
06691193
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates to computer architecture. In particular, the invention relates to multiprocessor systems.
2. Description of Related Art
In a multiprocessor system, several processors are connected to a bus to communicate with each other and with other devices. A processor that has control of the bus is referred to as a master. Examples of a master include central processing unit (CPU), digital signal processor (DSP), and direct memory access (DMA) controller. A device that can only respond to a bus operation (e.g., read, write) initiated by a master is referred to as a slave. Examples of a slave include memory device, serial input/output device, and universal asynchronous receiver and transceiver (UART).
In a typical multiprocessor system, there are several masters and slaves. The masters usually have to compete for the use of the bus. When a master is using the bus, other masters have to wait. The problem is even more severe when several masters want to access several slaves at the same time.
Therefore, there is a need to have a technique to utilize the bus efficiently.
SUMMARY
The present invention is a method and apparatus to provide efficient access to multiple slave devices via a plurality of slave buses. In one embodiment of the present invention, a slave interface circuit is coupled between one of P slave devices and K slave buses. The slave interface circuit includes a slave access circuit and a slave bus decoder. The slave access circuit provides access to the one of P slave devices from one of N master processors via a system bus controller and K slave buses. The K slave buses are configured to couple to the P slave devices. The system bus controller dynamically maps address spaces of the P slave devices. The slave bus decoder enables the one of the P slave devices to connect to one of the K slave buses when the one of the P slave devices is addressed by the one of the N master processors. The slave bus decoder is controlled by the system bus controller. In another embodiment of the present invention, the system bus controller includes an arbiter, a mapping circuit, and a switching circuit. The arbiter arbitrates access requests from N master processors via N master buses and generates arbitration signals. The mapping circuit stores mapping information to dynamically map an address space of P slave devices coupled to K slave buses based on the arbitration signals. The switching circuit connects the N master buses to K slave buses based on the arbitration signals and the mapping information.
REFERENCES:
patent: 5060141 (1991-10-01), Wakatani
patent: 5867645 (1999-02-01), Olarig
patent: 6081874 (2000-06-01), Carpenter et al.
patent: 6247100 (2001-06-01), Drehmel et al.
patent: 6496890 (2002-12-01), Azevedo et al.
patent: 6535941 (2003-03-01), Kruse
Kim Simon S.
Wang Sheng Hung
Blakely , Sokoloff, Taylor & Zafman LLP
Sony Corporation
Vo Tim
LandOfFree
Efficient bus utilization in a multiprocessor system by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Efficient bus utilization in a multiprocessor system by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Efficient bus utilization in a multiprocessor system by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3295902