Efficient buffer management in a multi-threaded network...

Details Efficient buffer management in a multi-threaded network... Efficient buffer management in a multi-threaded network...

2011-06-28

2011-06-28

Tseng, Cheng-Yuan (Department: 2184)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S057000

Reexamination Certificate

active

07970963

ABSTRACT:
Some embodiments of the present invention provide a system for receiving packets on a multi-threaded computing device which uses a memory-buffer-usage scorecard (MBUS) to enable multiple hardware threads to share a common pool of memory buffers. During operation, the system can identify a memory-descriptor location for posting a memory descriptor for a memory buffer. Next, the system can post the memory descriptor for the memory buffer at the memory-descriptor location. The system can then update the MBUS to indicate that the memory buffer is in use. Next, the system can store a packet in the memory buffer, and post a completion descriptor in a completion-descriptor location to indicate that the packet is ready to be processed. If the completion-descriptor indicates that the memory buffer is ready to be reclaimed, the system can reclaim the memory buffer, and update the MBUS to indicate that the memory buffer has been reclaimed.

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