Efficient bridge architecture for handling multiple write...

Details Efficient bridge architecture for handling multiple write... Efficient bridge architecture for handling multiple write...

1999-04-01

2001-05-08

Thai, Xuan M. (Department: 2181)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S052000, C710S056000

Reexamination Certificate

active

06230228

ABSTRACT:

FIELD OF THE INVENTION
This invention is generally related to electronic systems having a bridge, and more particularly to bridge architectures for handling multiple write transactions simultaneously.
BACKGROUND
High performance electronic systems such as those used for computer network servers and mass storage applications often feature a number of physically separate buses that allow a greater number of peripheral devices such as network interface controllers and disk controllers to be part of the system. A bridge combines the two buses into one logical bus, so that a device on one bus can readily communicate with a device on the other bus through the bridge. Communication between two devices on opposite sides of the bridge occurs as follows. A device known as the initiator presents a request for a write or read transaction on an initiating bus. The request specifies the address of a target device on a target bus on the opposite side of the bridge. The bridge which is coupled between the initiating and target buses has been previously configured to recognize such a request.
A two part transaction occurs when the bridge claims the request on the initiating bus, and subsequently transports the transaction onto the target bus. For instance, with a posted write transaction, the bridge accepts a write data packet from the initiator, and then signals a termination to disconnect the initiator and end the transaction on the initiating side. The data packet is temporarily stored in a data queue of the bridge. When the bridge thereafter acquires the target bus in a new transaction, the data packet is forwarded from the queue to the target. In systems that comply with the popular Peripheral Component Interconnect (PCI) Local Bus Specification, Rev. 2.1, Jun. 1, 1995, the posted write transaction is normally a write to memory or a memory-mapped location. For further information on such transactions, the reader is referred to the
i
960
® Rx I/O Microprocessor Developer's Manual
, April 1997, Intel Corp. Order No. 272736-002, chapter 15, PCI-to-PCI bridge unit.
Typically, conventional PCI bridges have been designed so that only a single posted write transaction, in a given direction through the bridge, can be pending in the bridge. Such bridges are used in a variety of different system applications that may have different data traffic patterns. For instance, in a network server application, the bridge is faced with the task of forwarding a large number of data packets from one bus to another, where each data packet may be relatively small. On the other hand, a mass storage application generates much larger packets but less frequently.
The conventional PCI bridge is often optimized at the design stage to more effectively handle a particular system application by engineering the size of its data queue. Optimizing at the design stage creates a problem, however, because it requires a number of different bridge designs each being specifically optimized for a dedicated system application, thus substantially increasing the cost of manufacturing bridges. Therefore, what is needed is a universal design that allows a bridge to dynamically adapt to changes in data traffic encountered in different system applications. Such a design should also make efficient use of the bridge's data queue, because the queue is a high speed and silicon-intensive realization and is therefore a relatively expensive component of the bridge.
SUMMARY
Accordingly, an embodiment of the invention is directed at a method of processing multiple write transactions using a bridge by storing first transaction information for a first transaction in a transaction queue of the bridge, storing first transaction data for the first transaction in a data queue of the bridge, storing second transaction information for a second transaction in the transaction queue, the transaction queue simultaneously containing the first and second transaction information. The method entails storing second transaction data for the second transaction in the data queue, the data queue simultaneously containing the first and second data. The mastering of the first and second transactions involves forwarding the first and second data from the data queue to one or more targets. Also, third transaction data for a third transaction can be stored in the data queue, the third data occupying the maximum available space in the data queue.
Other features and advantages of various embodiments of the invention will be apparent by referring to the detailed description, drawings, and claims below.


REFERENCES:
patent: 5694556 (1997-12-01), Neal et al.
patent: 5845145 (1998-12-01), James et al.
patent: 6047339 (2000-04-01), Su et al.
patent: 6070209 (2000-05-01), Hausauer
patent: 6108741 (2000-08-01), MacLaren et al.

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